The new generation of PowerPC VMEbus front end computers for the CERN SPS and LEP accelerators control system

The CERN SPS and LEP PowerPC project is aimed at introducing a new generation of PowerPC VMEbus processor modules running the LynxOS real-time operating system. This new generation of front end computers using the state-of-the-art microprocessor technology will first replace the obsolete Xenix PC based systems (about 140 installations) successfully used since 1988 to control the LEP accelerator. The major issues addressed in the scope of this large scale project are the technical specification for the new PowerPC technology, the re-engineering aspects, the interfaces with other CERN wide projects, and the set up of a development environment. This project offers also support for other major SPS and LEP projects interested in the PowerPC microprocessor technology

Using Relocatable Bitstreams for Fault Tolerance

This research develops a method for relocating reconfigurable modules on the Virtex-II (Pro) family of Field Programmable Gate Arrays (FPGAs). A bitstream translation program is developed which correctly changes the location of a partial bitstream that implements a module on the FPGA. To take advantage of relocatable modules, three fault-tolerance circuit designs are developed and tested. This circuit can operate through a fault by efficiently removing the faulty module and replacing it with a relocated module without faults. The FPGA can recover from faults at a known location, without the need for external intervention using an embedded fault recovery system. The recovery system uses an internal PowerPC to relocate the modules and reprogram the FPGA. Due to the limited architecture of the target FPGA and Xilinx tool errors, an FPGA with automatic fault recovery could not be demonstrated. However, the various components needed to do this type of recovery have been implemented and demonstrated individually

A methodology for analyzing commercial processor performance numbers

The wealth of performance numbers provided by benchmarking corporations makes it difficult to detect trends across commercial machines. A proposed methodology, based on statistical data analysis, simplifies exploration of these machines' large datasets

The new generation of PowerPC VMEbus front end computers for the CERN SPS and LEP accelerators system

The CERN SPS and LEP PowerPC project is aimed at introducing a new generation of PowerPC VMEbus processor modules running the LynxOS real-time operating system. This new generation of front end computers using the state-of-the-art microprocessor technology will first replace the obsolete XENIX PC based systems (about 140 installations) successfully used since 1988 to control the LEP accelerator. The major issues addressed in the scope of this large scale project are the technical specification for the new PowerPC technology, the re-engineering aspects, the interfaces with other CERN wide projects, and the set up of a development environment. This project offers also support for other major SPS and LEP projects interested in the PowerPC microprocessor technology

Microprocessor Implementation of Autoregressive Analysis of Process Sensor Signals

Automated signal analysis can help for effective system surveillance and also to analyze the dynamic behavior of the system such as impulse response, step response etc. Autoregressive analysis is a parametric technique widely used for system surveillance and diagnosis. The main aim objective of this research work is to develop an embedded system for autoregressive analysis of sensor signals in an online fashion for monitoring system parameters. This thesis presents the algorithm, data representation and performance of the optimized microprocessor implementation of autoregressive analysis. In this work an autoregressive (AR) model is generated as a solution to a linear system of equations called Yule-Walker linear equations. The generated model is then implemented on Motorola PowerPC MPC555 processor. The embedded software for autoregressive analysis is written in the C programming language using fixed point arithmetic. It includes estimation of the autoregressive parameters, estimation of the noise variance recursively using the AR parameters, determination of the optimal model order and the model validation

Study and development of a software implemented fault injection plug-in for the Xception tool/powerPC 750

Estágio realizado na Critical Software e orientado pelo Eng.º Ricardo BarbosaTese de mestrado integrado. Engenharia Informática e Computação. Faculdade de Engenharia. Universidade do Porto. 200