Efficient Test Set Modification for Capture Power Reduction

The occurrence of high switching activity when the response to a test vector is captured by flipflops in scan testing may cause excessive IR drop, resulting in significant test-induced yield loss. This paper addresses the problem with a novel method based on test set modification, featuring (1) a new constrained X-identification technique that turns a properly selected set of bits in a fullyspecified test set into X-bits without fault coverage loss, and (2) a new LCP (low capture power) X-filling technique that optimally assigns 0’s and 1’s to the X-bits for the purpose of reducing the switching activity of the resulting test set in capture mode. This method can be readily applied in any test generation flow for capture power reduction without any impact on area, timing, test set size, and fault coverage

Improving elevation resolution in phased-array inspections for NDT

The Phased Array Ultrasonic Technique (PAUT) offers great advantages over the conventional ultrasound technique (UT), particularly because of beam focusing, beam steering and electronic scanning capabilities. However, the 2D images obtained have usually low resolution in the direction perpendicular to the array elements, which limits the inspection quality of large components by mechanical scanning. This paper describes a novel approach to improve image quality in these situations, by combining three ultrasonic techniques: Phased Array with dynamic depth focusing in reception, Synthetic Aperture Focusing Technique (SAFT) and Phase Coherence Imaging (PCI). To be applied with conventional NDT arrays (1D and non-focused in elevation) a special mask to produce a wide beam in the movement direction was designed and analysed by simulation and experimentally. Then, the imaging algorithm is presented and validated by the inspection of test samples. The obtained images quality is comparable to that obtained with an equivalent matrix array, but using conventional NDT arrays and equipments, and implemented in real time.Fil: Brizuela, Jose David. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Camacho, J.. Consejo Superior de Investigaciones Científicas; EspañaFil: Cosarinsky, Guillermo Gerardo. Comisión Nacional de Energía Atómica; ArgentinaFil: Iriarte, Juan Manuel. Comisión Nacional de Energía Atómica; ArgentinaFil: Cruza, Jorge F.. Consejo Superior de Investigaciones Científicas; Españ

Attention Gated Networks: Learning to Leverage Salient Regions in Medical Images

We propose a novel attention gate (AG) model for medical image analysis that automatically learns to focus on target structures of varying shapes and sizes. Models trained with AGs implicitly learn to suppress irrelevant regions in an input image while highlighting salient features useful for a specific task. This enables us to eliminate the necessity of using explicit external tissue/organ localisation modules when using convolutional neural networks (CNNs). AGs can be easily integrated into standard CNN models such as VGG or U-Net architectures with minimal computational overhead while increasing the model sensitivity and prediction accuracy. The proposed AG models are evaluated on a variety of tasks, including medical image classification and segmentation. For classification, we demonstrate the use case of AGs in scan plane detection for fetal ultrasound screening. We show that the proposed attention mechanism can provide efficient object localisation while improving the overall prediction performance by reducing false positives. For segmentation, the proposed architecture is evaluated on two large 3D CT abdominal datasets with manual annotations for multiple organs. Experimental results show that AG models consistently improve the prediction performance of the base architectures across different datasets and training sizes while preserving computational efficiency. Moreover, AGs guide the model activations to be focused around salient regions, which provides better insights into how model predictions are made. The source code for the proposed AG models is publicly available.Comment: Accepted for Medical Image Analysis (Special Issue on Medical Imaging with Deep Learning). arXiv admin note: substantial text overlap with arXiv:1804.03999, arXiv:1804.0533

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US