On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

On mismatch in the deep sub-micron era-from physics to circuits

Ahstract-Rapid decrease in feature sizes has increasingly accentuated the importance of matching between transistors. Deep submicron designs will further emphasize the need to focus on the effects of mismatch. Furthermore, increased efforts on high level analog device modeling will necessitate accompanying mismatch simulation and measurement methods. The deep sub-micron era forces circuit designers to learn more about the physim and the technology of transistors, This study intraduces a method and assists circuit designers in including this method in their traditional design flow of circuits. By proposing a solution to the problem of building a modeling bridge between transistor mismatch and circuit response to it, we hope to enable designers to incorporate low level mismatch information in their higher level design

Standard Transistor Array (STAR). Volume 1: Placement technique

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties

Multiprocessing techniques for unmanned multifunctional satellites Final report,

Simulation of on-board multiprocessor for long lived unmanned space satellite contro

Submicron Systems Architecture: Semiannual Technical Report

No abstract available

Inkjet printed metal oxide thin film transistors incorporating polyethyleneimine

Fully inkjet printed fabrication of thin film transistors (TFTs) is desirable to enable reproducible, high throughput, low cost production of electronics under mild conditions. However, TFT devices fabricated from printable materials typically exhibit inferior performance to those of non-printed. For example, there is a lack of well performing source-drain electrode materials for metal oxide semiconductors. In contrast to vacuum-deposited Al, printed Ag has a high contact resistance and work function, with poor charge carrier injection to the semiconductor. Therefore, there is a requirement to improve electrical performance of TFTs incorporating printed electrode material such as Ag. The approach to achieve this through this work is by inclusion of an inkjet printed thin film of polyethyleneimine (PEI) at the interface between semiconductor and source-drain contacts. PEI contains tertiary amine groups, which possess lone pairs of electrons available to assist charge injection and lower the interfacial resistance. Two sets of reference devices were prepared, both with inkjet printed In2O3 semiconductor. One set was fabricated by vacuum deposition of Al for source drain electrodes, the other set with inkjet printed Ag source drain contact electrodes. The solution-based processing method limits the thermal budget to 300°C. Devices with Al electrodes provided charge carrier saturation mobility (μsat) of 4.3 ± 0.93 cm2 V-1 s-1, whereas those with Ag contacts exhibited an expected lower μsat of 8.0·10-3 ± 3.9·10-3 cm2 V-1 s-1. Addition of an inkjet printed interfacial thin film containing PEI between the semiconductor and Ag contact electrodes significantly increased the μsat to 3.1 ± 0.53 cm2 V-1 s-1. Interfacial engineering in this work yielded TFTs possessing printed Ag contacts that display electrical performance comparable with devices incorporating vacuum-deposited Al contacts. The impact of this result is the possibility for high performance fully printed TFTs. Development of this fabrication route might facilitate low temperature solution based roll-to-roll production of electrical components containing fully inkjet printed TFT devices

Design of a process monitor and of peripheral circuits enabling the characterisation of CMOS 45nm Ultra Low Power and Litho Friendly optimised standard cells

L’evoluzione della tecnologia CMOS è caratterizzata dallo scaling delle dimensioni dei dispositivi e dalla riduzione del consumo di potenza. Dal momento che le difficoltà di realizzazione aumentano al diminuire delle dimensioni, nei nodi tecnologici più recenti la velocità del processo di scaling sta diminuendo. Uno dei maggiori problemi causati dalla riduzione delle dimensioni dei dispositivi è la variabilità del processo di fabbricazione. L’obiettivo di questo progetto è quello di ridurre gli effetti che la variabilità del processo di realizzazione nel nodo tecnologico CMOS 45 nm ha sulle prestazioni della logica digitale, grazie a metodi di design non convenzionali. In questo progetto è stato realizzato un testchip per studiare e quantificare i vantaggi, in termini di prestazioni, ottenuti tramite la progettazione di librerie standard-like ottimizzate secondo canoni di litho-friendliness (LF) e ultra low power (ULP). Le standard cells LF utilizzano layout estremamente regolari. Le standard cells ULP sono progettate per operare con tensioni di alimentazioni notevolmente ridotte. Il fine principale del testchip sta nell’ottenere una panoramica della variabilità locale e globale di parametri significativi nella progettazione digitale: ad esempio la frequenza di lavoro e il consumo di potenza. Inoltre, nel testchip sono stati realizzati alcuni circuiti originali per il monitoraggio della qualità del processo di fabbricazione. The evolution of the CMOS technology is characterized by the scaling of transistors size and by the reduction of their power dissipation. In the last technology nodes the speed of the scaling process is decreasing, since the complexity of the technology increases with its size reduction. One of the main issues caused by the shrinking of the transistor size is the variability of the fabrication process. The target of this project is to reduce the effects of the variability of the realisation process in a CMOS 45 nm technology node in digital circuits performances, using unconventional design methods. A testchip is realised in this project to investigate and to quantify the improvement of the circuit performances obtained through the design of dedicated litho-friendly (LF) and of the Ultra Low Power (ULP) standard-like libraries. The LF standard cells libraries are optimised for lithography using ultra regular layout styles. The ULP standard cells library is optimised to operate at extremely low supply voltage. The main aim of the testchip is to get insight into the local and the global variability of relevant parameters for digital design, such as operating frequency and power consumption. In this testchip some structures are also included, to develop some innovative circuits that should help to monitor the quality of the technology process

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics