A parametric study on the effects of the variations in line width on the circuit model parameters of a planar spiral inductor on GaAs

The increasing demands for low cost radio frequency integrated circuits (RFIC’s) has generated great attention in on-chip passive components. A spiral inductor is an important passive component for many radio frequency circuits such as low noise amplifiers, mixers, switches, and voltage controlled oscillators. Considerable effort has gone into the design and modeling of the spiral inductor, however, very little research has investigated the effects due to the errors introduced into the spiral inductor modeling. This research investigates the effects of variations in conductor line width on equivalent circuit model of planar rectangular spiral inductors. A parametric study is performed where a full wave electromagnetic simulator, Sonnet TM, is used to simulate several sets of inductors on Gallium Arsenide (GaAs) substrate having different dimensions. The scattering parameters of a particular inductor were simulated over the desired frequency range. These simulated scattering parameters are used to extract the equivalent circuit model parameters using optimization process. The extracted inductor model parameters are validated through the existing physics based formulae. the simulation results reveals that variations in the conductor line width affect every parameters in the equivalent circuit model of the inductor i.e. the series inductance, the series resistance, the capacitance between the inductor turns. Change in series inductance due to the variations in the conductor line width is nearly a linear function of the nominal inductance. Variation in series resistance is an exponential function of nominal conductor width. Change in line to line capacitance due to variations in conductor line width is an exponential function of nominal spacing between conductors. Finally, variations in conductor line width have no or little effects on substrate capacitance. Curve fitting techniques are utilized to extract simple equations useful for estimating the changes in the circuit model parameters with respect to the variation in conductor line width. These equations advantageous to the RFIC’s designer since the inductor equivalent circuit model parameters can easily be modified to account for variations in conductor line width and also they can be used during circuit design optimization to explore inductor space

Generalized analytical model for RF planar inductors using a segmentation technique

The planar coil inductor has become a very critical circuit component in RF mixed signal application where it can reside either on the package or in the chip. However, there is no clear methodology to accurately analyze the behavior of the inductor over a broad range of frequencies and for obtaining a particular physical layout for a required value of inductance. At present, it has been done by full wave solvers, approximate quasistatic analysis, and lumped element equivalent circuits, each with its own advantages and limitations. This work presents an analytical model based on a segmentation method in conjunction with a Green\u27s function for a power/ground plane model. This method has been used to obtain analytical closed form solution for planar coil inductors of two popular shapes, the rectangular and circular configurations. The model includes a ground plane and the coil configuration such as spacing and line width, and the material characteristic such as conductivity of the metal layer and the dielectric parameters. It is a frequency dependant solution that includes the resonant modes in the cavity formed by the inductor and the ground plane. This method has been applied successfully to rectangular and circular coil inductors of different dimensions where there is excellent agreement with full wave solvers. Inductors on a package and in a chip have been fabricated and experimental results show excellent agreement to predicted values obtained from this analytical work. Also presented in this work is a comparison of popular EM full wave solvers and two quasistatic methods, the advantages and limitations of each have been discussed. Experimental techniques to measure for RF silicon IC Inductors have been developed

3D modeling and integration of current and future interconnect technologies

Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit performance and signal integrity in the circuit design phase. A full phase simulation for performance estimation of a large-scale circuit not only require a massive computational resource but also need a lot of time to produce acceptable results. The estimation of performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect capacitance. So, an accurate model for interconnect capacitance can be used in the circuit CAD (computer-aided design) tools for circuit performance estimation before circuit fabrication which reduces the computational resource requirement as well as the time constraints. We propose a new capacitance models for interconnect lines in multilevel interconnect structures by geometrically modeling the electrical flux lines of the interconnect lines. Closed-form equations have been derived analytically for ground and coupling capacitance. First, the capacitance model for a single line is developed, and then the new model is used to derive expressions for the capacitance of a line surrounded by neighboring lines in the same and the adjacent layers above and below. These expressions are simple, and the calculated results are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias. Signal speed in current digital systems depends mainly on the delay of interconnects. To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit (vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to ensure much smaller interconnect lengths, and lower delay and power consumption compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit performance depends on different electrical parameters (capacitance, resistance, inductance) of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance, resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived from the physical shape and the size of the TSV. The modeling approach is comprehensive and includes both the cylindrical and tapered TSVs as well as the bumps. On-chip integration of inductors has always been very challenging. However, for sub- 14nm on-chip applications, large area overhead imposed by the on-chip capacitors and inductors has become a more severe concern. To overcome this issue and ensure power integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The proposed TSV based inductor has the potential to achieve both high density and high performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV based inductor is also presented. The implementation of the VCO is intended to study the feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor

Copper / low-k technological platform for the fabrication of high quality factor above-IC passive devices

Modern communication devices demand challenging specifications in terms of miniaturization, performance, power consumption and cost. Every new generation of radio frequency integrated circuits (RF-ICs) offer better functionality at reduced size, power consumption and cost per device and per integrated function. Passive devices (resistors, inductors, capacitors, antennas and transmission lines) represent an important part of the cost and size of RF circuits. These components have not evolved at the same level of the transistor devices, especially because their performance is strongly degenerated when they scale down in size. The low resistivity silicon used to build the transistors also imposes prohibitive levels of RF losses to these passive devices. Radio frequency microelectromechanical systems (RF MEMS) are enabling technologies capable to bring significant improvement in the electrical performances and expressive size and cost reduction of these functions, with unparallel introduction of new functionalities, unimaginable to attain when using bulky, externally connected discrete components. High quality factor (Q) inductors are amongst ones of the most needed components in RF circuits and at the same time ones that are most affected by thin metallization and substrate related losses, demanding considerable research effort. This thesis presents a contribution toward the development of thick metal fabrication technologies, covering also the design, modeling and characterization of high quality factor and high self-resonant frequency (SRF) RF MEMS passive devices, with a special emphasis on spiral inductors. A new approach using damascene-like interconnect fabrication steps associated to low κ dielectrics (polyimide), highly-conductive thick copper electroplating, chemical mechanical polishing (CMP) and tailored substrate properties delivered quality factors in excess of 40 and self resonant frequencies in excess of 10 GHz, performances in the current state-of-the-art for integrated spiral inductors built on top of silicon wafers. Furthermore, the developed process steps are compatible with back-end processing used to fabricate modern IC interconnects and have a low thermal budget (< 250 °C), what makes it a good choice to build above-IC passives without degenerating the performance of passivated RF-CMOS circuits. Deep reactive ion etching (DRIE) of quartz substrates was also studied for the fabrication of spiral inductors, offering excellent RF performances (Q exceeding 40 and SRF exceeding 7 GHz). A new doubly-functional quartz packaging concept for RF MEMS devices was developed. This technique process both sides of the packaging wafer: the top is used to embed high quality factor copper inductors while the bottom is thermo-mechanically bonded to another RF MEMS wafer, offering a semi-hermetic SU-8 epoxy-based seal. The bonding process was optimized for high yield, to be compatible with SF6-plasma-released MEMS and to present low level of RF losses. Band pass filters for the GSM (1.8 GHz) and WLAN (5.2 GHz) standards were fabricated and characterized by RF measurements and full wave electromagnetic simulations. Although further development is need in order to predict the frequency response accurately, insertion losses as low as 1.2 dB were demonstrated, levels that cannot be usually attained using on-chip passives. Systematic analysis, RF measurements, electromagnetic simulations and equivalent circuit extraction were used to model the behavior of the fabricated devices and establish a methodology to deliver optimum performances for a given technological profile and specified performance targets (quality factor, inductance and frequency bandwidth). A simple yet accurate physics-based analytical model for spiral inductors was developed and proved to be accurate in terms of loss estimation for thick metal layers. This model is capable to accurately describe the frequency-dependent behavior of the device below its first resonant frequency over a large device design space. The model was validated by both measurements and full wave electromagnetic simulations and is well suited to perform numeric optimization of designs. The proposed models were also systematized in a Matlab® toolbox

Modeling and characterization of on-chip interconnects, inductors and transformers

Ph.DNUS-SUPELEC JOINT PH.D. PROGRAMM

Design, modelization and realization of integrated inductive components for low power supplies and microsystems

Full integration of energy conversion devices for compact power supply circuits is still encountering strong technological locks, especially to integrate passive inductive and capacitive components. The increasing working frequency of those devices, which already reaches 1 Megahertz, would enable the size reduction of passive components and then their integration. Nevertheless, losses, which highly depend on frequency and technology, may complicate or even stop this increase.\ud The objective of this thesis is the systematic study of integrated inductors structures through the developing of precise modeling and simulating methods on the frequency range from 0Hz to 1GHz. First, an analytic model based on PEEC (Partial Element Equivalent Circuit) method has been developed. This modeling approach has been adapted to the studied components: rotational symmetry, not negligible section conductors, inhomogeneous media, etc… The final model splits the physical study of the component into two steps: electromagnetic computations on subparts of the set (partial elements) and global frequency response calculus with the equivalent electrical models of the subparts. A full process for the technological realization of inductive components has also been achieved in order to experimentally verify the modeling. The improvement of design resolution and increase of copper electroplating thickness, as planarization of conductor levels with SU8 resin have been specifically studied. Those overhangs have permitted the realization of multilevel and multiconductor inductors which present good features at high frequency. Finally, the characterization of prototypes at low frequency has been enabled by the realization of an impedance measurement bench we developed for the range from 40Hz to 110MHz and high frequency characterizations have been performed with a network analyzer. This work has been completed by the development of a very fast computing analytical model for the calculus of the magnetic field in integrated inductors. This method has been used to find the repartition of the magnetic field generated by integrated planar magnetic actuators excited by a DC current for a microsystems and microfluidics application.---------------------------------------------------------------L’intégration complète des dispositifs de conversion d’énergie destinés à créer des circuits d’alimentation compacts se heurte encore aujourd’hui à des contraintes technologiques fortes sur l’intégration des composants passifs inductifs et capacitifs. La fréquence de fonctionnement de ces dispositifs, d’ores et déjà de l’ordre du MHz, en augmentant pourrait réduire la taille de ces composants passifs et donc permettre leur intégration. Cependant, les pertes fortement liées à la fréquence et à la technologie, freinent encore cette augmentation.\ud Cette thèse a pour objectif l’étude systématique de structures d’inductances intégrées à travers le développement d’une modélisation accompagnée de simulations précises pour le développement d’une méthodologie de simulation valable sur la plage de fréquence de 0Hz à 1GHz. Pour cela, un modèle analytique basé sur la méthode PEEC (Partial Element Equivalent Circuit) a d’abord été développé. Ce type de modèle a du être adapté aux topologies des composants étudiés : symétrie cylindrique, conducteurs de section non négligeable, milieux non homogènes… Ce modèle décompose l’étude du composant en deux étapes : calculs électromagnétiques menés sur des sous-parties du composant (éléments partiels) et calcul de la réponse fréquentielle globale à partir de modèles électriques des éléments partiels. Un procédé complet de réalisation technologique des composants inductifs a également été mis au point en parallèle afin de valider expérimentalement la modélisation. L’amélioration de la résolution des motifs et l’augmentation de l’épaisseur des dépôts lors des étapes de croissance électrolytique du cuivre, ainsi que la planarisation des niveaux de conducteurs avec de la résine SU8 ont fait l’objet d’études spécifiques. Ces avancées ont permis la réalisation de selfs multibrin et multiniveau qui présentent des caractéristiques électriques intéressantes en haute fréquence. Enfin, la caractérisation des prototypes en basse fréquence a été rendue possible par la mise en oeuvre d’un banc de mesure d’impédance pour la gamme de fréquence de 40 Hz à 110MHz et des caractérisations en haute fréquence effectuées à l’aide d’un analyseur de réseau. Ces travaux ont été complétés par la mise au point d’une méthode analytique de calcul du champ magnétique. Les calculs permettent de prédire la répartition du champ magnétique généré par des actionneurs magnétiques planaires intégrés excités en courant continu

Characterization and design of CMOS components for microwave and millimeter wave applications

Ph.DDOCTOR OF PHILOSOPH

Design of Wireless Power Transfer and Data Telemetry System for Biomedical Applications

With the advancement of biomedical instrumentation technologies sensor based remote healthcare monitoring system is gaining more attention day by day. In this system wearable and implantable sensors are placed outside or inside of the human body. Certain sensors are needed to be placed inside the human body to acquire the information on the vital physiological phenomena such as glucose, lactate, pH, oxygen, etc. These implantable sensors have associated circuits for sensor signal processing and data transmission. Powering the circuit is always a crucial design issue. Batteries cannot be used in implantable sensors which can come in contact with the blood resulting in serious health risks. An alternate approach is to supply power wirelessly for tether-less and battery- less operation of the circuits.Inductive power transfer is the most common method of wireless power transfer to the implantable sensors. For good inductive coupling, the inductors should have high inductance and high quality factor. But the physical dimensions of the implanted inductors cannot be large due to a number of biomedical constraints. Therefore, there is a need for small sized and high inductance, high quality factor inductors for implantable sensor applications. In this work, design of a multi-spiral solenoidal printed circuit board (PCB) inductor for biomedical application is presented. The targeted frequency for power transfer is 13.56 MHz which is within the license-free industrial, scientific and medical (ISM) band. A figure of merit based optimization technique has been utilized to optimize the PCB inductors. Similar principal is applied to design on-chip inductor which could be a potential solution for further miniaturization of the implantable system. For layered human tissue the optimum frequency of power transfer is 1 GHz for smaller coil size. For this reason, design and optimization of multi-spiral solenoidal integrated inductors for 1 GHz frequency is proposed. Finally, it is demonstrated that the proposed inductors exhibit a better overall performance in comparison with the conventional inductors for biomedical applications

A parametric study on the effects of the variations in line width on the circuit model parameters of a planar spiral inductor on GaAs

The increasing demands for low cost radio frequency integrated circuits (RFIC’s) has generated great attention in on-chip passive components. A spiral inductor is an important passive component for many radio frequency circuits such as low noise amplifiers, mixers, switches, and voltage controlled oscillators. Considerable effort has gone into the design and modeling of the spiral inductor, however, very little research has investigated the effects due to the errors introduced into the spiral inductor modeling. This research investigates the effects of variations in conductor line width on equivalent circuit model of planar rectangular spiral inductors. A parametric study is performed where a full wave electromagnetic simulator, Sonnet TM, is used to simulate several sets of inductors on Gallium Arsenide (GaAs) substrate having different dimensions. The scattering parameters of a particular inductor were simulated over the desired frequency range. These simulated scattering parameters are used to extract the equivalent circuit model parameters using optimization process. The extracted inductor model parameters are validated through the existing physics based formulae. the simulation results reveals that variations in the conductor line width affect every parameters in the equivalent circuit model of the inductor i.e. the series inductance, the series resistance, the capacitance between the inductor turns. Change in series inductance due to the variations in the conductor line width is nearly a linear function of the nominal inductance. Variation in series resistance is an exponential function of nominal conductor width. Change in line to line capacitance due to variations in conductor line width is an exponential function of nominal spacing between conductors. Finally, variations in conductor line width have no or little effects on substrate capacitance. Curve fitting techniques are utilized to extract simple equations useful for estimating the changes in the circuit model parameters with respect to the variation in conductor line width. These equations advantageous to the RFIC’s designer since the inductor equivalent circuit model parameters can easily be modified to account for variations in conductor line width and also they can be used during circuit design optimization to explore inductor space