Computer-Aided Design of Switched-Capacitor Filters

This thesis describes a series of computer methods for the design of switched-capacitor filters. Current software is greatly restricted in the types of transfer function that can be designed and in the range of filter structures by which they can be implemented. To solve the former problem, several new filter approximation algorithms are derived from Newton's method, yielding the Remez algortithm as a special case (confirming its convergency properties). Amplitude responses with arbitrary passband shaping and stopband notch positions are computed. Points of a specified degree of tangency to attenuation boundaries (touch points) can be placed in the response, whereby a family of transfer functions between Butterworth and elliptic can be derived, offering a continuous trade-off in group delay and passive sensitivity properties. The approximation algorithms have also been applied to arbitrary group delay correction by all-pass functions. Touch points form a direct link to an iterative passive ladder design method, which bypasses the need for Hurwitz factorisation. The combination of iterative and classical synthesis methods is suggested as the best compromise between accuracy and speed. It is shown that passive ladder prototypes of a minimum-node form can be efficiently simulated by SC networks without additional op-amps. A special technique is introduced for canonic realisation of SC ladder networks from transfer functions with finite transmission at high frequency, solving instability and synthesis difficulties. SC ladder structures are further simplified by synthesising the zeros at +/-2fs which are introduced into the transfer function by bilinear transformation. They cause cancellation of feedthrough branches and yield simplified LDI-type SC filter structures, although based solely on the bilinear transform. Matrix methods are used to design the SC filter simulations. They are shown to be a very convenient and flexible vehicle for computer processing of the linear equations involved in analogue filter design. A wide variety of filter structures can be expressed in a unified form. Scaling and analysis can readily be performed on the system matrices with great efficiency. Finally, the techniques are assembled in a filter compiler for SC filters called PANDDA. The application of the above techniques to practical design problems is then examined. Exact correction of sinc(x), LDI termination error, pre-filter and local loop telephone line weightings are illustrated. An optimisation algorithm is described, which uses the arbitrary passband weighting to predistort the transfer function for response distortions. Compensation of finite amplifier gain-bandwidth and switch resistance effects in SC filters is demonstrated. Two commercial filter specifications which pose major difficulties for traditional design methods are chosen as examples to illustrate PANDDA's full capabilities. Significant reductions in order and total area are achieved. Finally, test results of several SC filters designed using PANDDA for a dual-channel speech-processing ASIC are presented. The speed with which high-quality, standard SC filters can be produced is thus proven

Analogue filter networks: developments in theory, design and analyses

Not availabl

Modern VLSI Analogue Filter Design: Methodology and Software Development

This thesis describes various approaches for the design of modern analogue filters and provides a practical filter and equaliser design aids system XFILT. The thesis begins by placing the analogue filter design technique and software into a historical and technology perspective. The evolution of the analogue filter is traced from early work, through the passive-RLC to transconductor-C and switched-current realisations. The software development in VLSI analogue filter automation is reviewed. For SC filter design, a cascade SC design approach which includes a novel pole-zero pairing method and a comprehensive comparison of SC filter realisation using different biquads are presented. Very useful guidelines for the choice of a suitable biquad structure according to the nature of the filter problem are presented. The canonical realisations of SC filter are studied. The multirate SC system design is described. Several strategies and the algorithms for multirate SC system design are proposed. In transconductor-C filter design research, the definition of a canonical ladder based transconductor-C filter is introduced, and two canonical ladder based transconductor-C filter design approaches are proposed. The ladder based transconductor-C equaliser design is also discussed. A practical video frequency transconductor-C filter and equaliser design is given to demonstrate the utility of the matrix design method and the design software. A new approach to realise exact ladder based SI filter with first and second generation memory cell has been proposed. The bilinear transformation is used in the design procedure. Eight different SI ladder based structures can be obtained for one prototype ladder. Therefore it provides SI filter designers with various circuit choices based on different requirement such as area, maximum ratio of transistor aspect ratio limit, sensitivity or noise performance. Techniques to improve dynamic range and reduce circuit parameter spread are also presented. The proposed approach is well suited for a computer compiler implementation. A suitability study of each decomposition method for different filtering applications is also carried out and a general guideline for the choice of different decomposition methods is obtained. A comparison study on SI filter sensitivity performance based on first generation and second generation memory cells is carried out. Using four filter examples, it is demonstrated that SI filters based on a second generation SI memory cell have good sensitivity performance. For SI filters based on first generation memory cells, it is shown that a high ratio of clock frequency to cutoff frequency in the lowpass case, or a high ratio of clock frequency to midband frequency in the bandpass case would introduce high sensitivity. A novel approach for SI ladder filter based on the S2I integrator is also proposed and a canonical realisation for SI filter based on S2I integrator is developed. Examination of SI equaliser design reveals that cascade structure is a better candidate than ladder based structure. Multirate SI filter system design is also studied. Finally, a very brief introduction to the assembly of the design methods in this thesis into a software package XHLT for VLSI analogue filter and equaliser design is given. The user aspects of XFILT have been discussed and various capabilities of XFILT are demonstrated. Several advanced facilities which remove traditional design limitations are illustrated. The philosophy of the system is explained. It is shown that the distinguished features of XFILT are Ease of Use. General Applicability, and Ease of Extension. The system structure is described and the graphics interface which acts both as user friendly interface and a system manager of all the software is outlined. Fabricated SC, transconductor-C, and SI filter and equaliser have been designed by using XFILT. The system is under further enhancement toward a commercial product

Design of adaptive analog filters for magnetic front-end read channels

Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem para canais de leitura em sistemas de gravação e reprodução de dados em suporte magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a 1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços muito significativos a nível mundial com o objectivo de se investigarem novas técnicas de realização de filtros em circuito integrado monolítico, especialmente em tecnologia CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização de soluções com as características desejadas. Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão de sinal bem como a escolha de bons modelos matemáticos para o tratamento da informação e a minimização de erro inerente às aproximações na conformidade aos princípios físicos dos dispositivos caracterizados. O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo, baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization) com base na igualização de sinal utilizando filtros integrados analógicos em tempo contínuo. Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo, dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa e análise de estruturas ideais no projecto de filtros recorrendo a representações no espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de circuitos de transcondutância para a implementação de filtros integrados analógicos em tempo contínuo. Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros no espaço de estados, correspondentes a duas soluções alternativas para a realização de um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem, para utilização num canal de leitura de dados em suporte magnético. Como parte constituinte destes filtros, apresenta-se uma técnica de realização de circuitos de transcondutância, e de realização de condensadores lineares usando matrizes de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se métodos de adaptação automática capazes de compensar os erros face aos valores nominais dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os quais apresentamos os resultados de simulação e de medição experimental obtidos. Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível de constituir uma solução para o controlo de posicionamento da cabeça de leitura em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo de igualação do canal de leitura. Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency filters. The motivation of this work was the search for filtering solutions for the readchannel in recording and reproduction of data on magnetic media systems, with costs and consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than the available circuits. Accordingly, as was done in this work, the rapid development of microelectronics technology raised very significant efforts worldwide in order to investigate new techniques for implementing such filters in monolithic integrated circuit, especially in CMOS technology (Complementary Metal Oxide Semiconductor). We present a comparative study on different hierarchical levels of the project, which led to the realization and characterization of solutions with the desired characteristics. In the first level, this study addresses the conceptual question of recording and transmission of signal and the choice of good mathematical models for the processing of information and minimization of error inherent in the approaches and in accordance with the principles of the characterized physical devices. The main work of this thesis is focused on the hierarchical levels of the architecture of the read channel and the integrated circuit implementation of its main block - the filtering block. At the architecture level of the read channel this work presents a comprehensive study on existing methodologies of adaptation and signal recovery of data on magnetic media. This project appears in the sequence of the proposed solution for a lowcost, low consumption, low voltage, low complexity, using CMOS digital technology for the performance of a DFE (Decision Feedback Equalization) based on the equalization of the signal using integrated analog filters in continuous time. At the project level of implementation of the filtering block and techniques for implementing filters and its building components, it was concluded that the technique based on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate for the implementation of very-high-frequency adaptive filters. We defined in this lower level, two sub-levels of depth study for this thesis, namely: research and analysis of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation of continuous time integrated analog filters. Following this study, we present and compare two filtering structures operating in the space of states, corresponding to two alternatives for achieving a realization of an adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a read-channel for magnetic media devices. As a constituent part of these filters, we present a technique for the realization of transconductance circuits and for the implementation of linear capacitors using arrays of MOSFET transistors for signal processing in very-high-frequency integrated circuits using sub-micrometric CMOS technology. We present methods capable of automatic adjustment and compensation for deviation errors in respect to the nominal values of the components inherent to the tolerances of the fabrication process, for which we present the simulation and experimental measurement results obtained. Also as a result of this study, is the presentation of a circuit that provides a solution for the control of the head positioning on recording/playback systems of data on magnetic media. The proposed block is an adaptive first-order filter, based on the same transconductance circuits and equalization techniques proposed and used in the implementation of the adaptive filter for the equalization of the read channel. This filter was designed and included in an integrated circuit (Jaguar) used to control the positioning of the read-head done for ATMEL company in Colorado Springs, and part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company