2,892 research outputs found
Testability Analysis of Synchronous Sequential Circuits Based On Structural Data
Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
Two novel evolutionary formulations of the graph coloring problem
We introduce two novel evolutionary formulations of the problem of coloring
the nodes of a graph. The first formulation is based on the relationship that
exists between a graph's chromatic number and its acyclic orientations. It
views such orientations as individuals and evolves them with the aid of
evolutionary operators that are very heavily based on the structure of the
graph and its acyclic orientations. The second formulation, unlike the first
one, does not tackle one graph at a time, but rather aims at evolving a
`program' to color all graphs belonging to a class whose members all have the
same number of nodes and other common attributes. The heuristics that result
from these formulations have been tested on some of the Second DIMACS
Implementation Challenge benchmark graphs, and have been found to be
competitive when compared to the several other heuristics that have also been
tested on those graphs.Comment: To appear in Journal of Combinatorial Optimizatio
Automatic test pattern generation for asynchronous circuits
The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer
scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes
inevitably part of the design process; a technique called design for test (DFT). Asynchronous
circuits have a number of desirable properties making them suitable for the challenges posed
by modern technologies, but are severely limited by the unavailability of EDA tools for DFT
and automatic test-pattern generation (ATPG).
This thesis is motivated towards developing test generation methodologies for asynchronous
circuits. In total four methods were developed which are aimed at two different fault models:
stuck-at faults at the basic logic gate level and transistor-level faults. The methods were
evaluated using a set of benchmark circuits and compared favorably to previously published
work.
First, ABALLAST is a partial-scan DFT method adapting the well-known BALLAST technique
for asynchronous circuits where balanced structures are used to guide the selection of
the state-holding elements that will be scanned. The test inputs are automatically provided
by a novel test pattern generator, which uses time frame unrolling to deal with the remaining,
non-scanned sequential C-elements. The second method, called AGLOB, uses algorithms
from strongly-connected components in graph graph theory as a method for finding the optimal
position of breaking the loops in the asynchronous circuit and adding scan registers. The
corresponding ATPG method converts cyclic circuits into acyclic for which standard tools can
provide test patterns. These patterns are then automatically converted for use in the original
cyclic circuits. The third method, ASCP, employs a new cycle enumeration method to find the
loops present in a circuit. Enumerated cycles are then processed using an efficient set covering
heuristic to select the scan elements for the circuit to be tested.Applying these methods to
the benchmark circuits shows an improvement in fault coverage compared to previous work,
which, for some circuits, was substantial. As no single method consistently outperforms the
others in all benchmarks, they are all valuable as a designerâs suite of tools for testing. Moreover,
since they are all scan-based, they are compatible and thus can be simultaneously used in
different parts of a larger circuit.
In the final method, ATRANTE, the main motivation of developing ATPG is supplemented by
transistor level test generation. It is developed for asynchronous circuits designed using a State
Transition Graph (STG) as their specification. The transistor-level circuit faults are efficiently
mapped onto faults that modify the original STG. For each potential STG fault, the ATPG tool
provides a sequence of test vectors that expose the difference in behavior to the output ports.
The fault coverage obtained was 52-72 % higher than the coverage obtained using the gate
level tests. Overall, four different design for test (DFT) methods for automatic test pattern generation
(ATPG) for asynchronous circuits at both gate and transistor level were introduced in this thesis.
A circuit extraction method for representing the asynchronous circuits at a higher level of
abstraction was also implemented.
Developing new methods for the test generation of asynchronous circuits in this thesis facilitates
the test generation for asynchronous designs using the CAD tools available for testing the
synchronous designs. Lessons learned and the research questions raised due to this work will
impact the future work to probe the possibilities of developing robust CAD tools for testing the
future asynchronous designs
Parallel Implementation of Efficient Search Schemes for the Inference of Cancer Progression Models
The emergence and development of cancer is a consequence of the accumulation
over time of genomic mutations involving a specific set of genes, which
provides the cancer clones with a functional selective advantage. In this work,
we model the order of accumulation of such mutations during the progression,
which eventually leads to the disease, by means of probabilistic graphic
models, i.e., Bayesian Networks (BNs). We investigate how to perform the task
of learning the structure of such BNs, according to experimental evidence,
adopting a global optimization meta-heuristics. In particular, in this work we
rely on Genetic Algorithms, and to strongly reduce the execution time of the
inference -- which can also involve multiple repetitions to collect
statistically significant assessments of the data -- we distribute the
calculations using both multi-threading and a multi-node architecture. The
results show that our approach is characterized by good accuracy and
specificity; we also demonstrate its feasibility, thanks to a 84x reduction of
the overall execution time with respect to a traditional sequential
implementation
Probabilistic Graphical Models on Multi-Core CPUs using Java 8
In this paper, we discuss software design issues related to the development
of parallel computational intelligence algorithms on multi-core CPUs, using the
new Java 8 functional programming features. In particular, we focus on
probabilistic graphical models (PGMs) and present the parallelisation of a
collection of algorithms that deal with inference and learning of PGMs from
data. Namely, maximum likelihood estimation, importance sampling, and greedy
search for solving combinatorial optimisation problems. Through these concrete
examples, we tackle the problem of defining efficient data structures for PGMs
and parallel processing of same-size batches of data sets using Java 8
features. We also provide straightforward techniques to code parallel
algorithms that seamlessly exploit multi-core processors. The experimental
analysis, carried out using our open source AMIDST (Analysis of MassIve Data
STreams) Java toolbox, shows the merits of the proposed solutions.Comment: Pre-print version of the paper presented in the special issue on
Computational Intelligence Software at IEEE Computational Intelligence
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