Spacelab system analysis: The modified free access protocol: An access protocol for communication systems with periodic and Poisson traffic

The protocol definition and terminal hardware for the modified free access protocol, a communications protocol similar to Ethernet, are developed. A MFA protocol simulator and a CSMA/CD math model are also developed. The protocol is tailored to communication systems where the total traffic may be divided into scheduled traffic and Poisson traffic. The scheduled traffic should occur on a periodic basis but may occur after a given event such as a request for data from a large number of stations. The Poisson traffic will include alarms and other random traffic. The purpose of the protocol is to guarantee that scheduled packets will be delivered without collision. This is required in many control and data collection systems. The protocol uses standard Ethernet hardware and software requiring minimum modifications to an existing system. The modification to the protocol only affects the Ethernet transmission privileges and does not effect the Ethernet receiver

Ethernet goes real-time: a survey on research and technological developments

Ethernet is the most popular LAN technology. Its low price and robustness, resulting from its wide acceptance and deployment, has created an eagerness to expand its responsibilities to the factory-floor, where real-time requirements are to be fulfilled. However, it is difficult to build a real-time control network using Ethernet, because its MAC protocol, the 1-persistent CSMA/CD protocol with the BEB collision resolution algorithm, has unpredictable delay characteristics. Many anticipate that the recent technological advances in Ethernet such as the emerging Fast/Gigabit Ethernet, micro-segmentation and full-duplex operation using switches will also enable it to support time-critical applications. This technical report provides a comprehensive look at the unpredictability inherent to Ethernet and at recent technological advances towards real-time operation

Modelling IEEE 802.11 CSMA/CA RTS/CTS with stochastic bigraphs with sharing

Stochastic bigraphical reactive systems (SBRS) is a recent formalism for modelling systems that evolve in time and space. However, the underlying spatial model is based on sets of trees and thus cannot represent spatial locations that are shared among several entities in a simple or intuitive way. We adopt an extension of the formalism, SBRS with sharing, in which the topology is modelled by a directed acyclic graph structure. We give an overview of SBRS with sharing, we extend it with rule priorities, and then use it to develop a model of the 802.11 CSMA/CA RTS/CTS protocol with exponential backoff, for an arbitrary network topology with possibly overlapping signals. The model uses sharing to model overlapping connectedness areas, instantaneous prioritised rules for deterministic computations, and stochastic rules with exponential reaction rates to model constant and uniformly distributed timeouts and constant transmission times. Equivalence classes of model states modulo instantaneous reactions yield states in a CTMC that can be analysed using the model checker PRISM. We illustrate the model on a simple example wireless network with three overlapping signals and we present some example quantitative properties

Improving IEEE 802.11 to Support Quality of Service in Wireless Networks

This paper investigates and describes the Quality of Services (QoS) provisioning techniques for IEEE 802.11 based networks, focusing on the Distributed Coordination Function (DCF). This paper propose better techniques to provide QoS by assigning new parameters to the DCF access method, involving the DCF Interframe Space (DIFS), backoff time and the maximum data packet size to high priority nodes, which will distinguish the high priority traffic from the low priority traffic to support QoS. A simulation is done using Network Simulator 2 (NS-2) and the expected output is then presented

Investigation of the consumer electronics bus

The objectives of this dissertation are to investigate the performance of the Consumer Electronics Bus (CEBus) and to develop a theoretical formulation of the Carrier Sense Multiple Access with Contention Detection and Contention Resolution (CSMA/CDCR) with three priority classes protocol utilized by the CEBus A new priority channel assigned multiple access with embedded priority resolution (PAMA/PR) theoretical model is formulated. It incorporates the main features of the CEBus with three priority classes. The analytical results for throughput and delay obtained by this formulation were compared to simulation experiments. A close agreement has been found thus validated both theory and simulation models Moreover, the performance of the CEBus implemented with two physical media, the power line (PL) and twisted pair (TP) communication lines, was investigated by measuring message and channel throughputs and mean packet and message delays. The router was modeled as a node which can handle three priority levels simultaneously. Satisfactory performance was obtained. Finally, a gateway joining the CEBus to ISDN was designed and its perfor-mance was evaluated. This gateway provides access to ISDN-based services to the CEBus. The ISDN and CEBus system network architecture, gateway wiring, and data and signaling interface between the CEBus and ISDN were designed, analyzed, and discussed. Again, satisfactory performance was found

Scalability of broadcast performance in wireless network-on-chip

Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors with hundreds or thousands of cores. The main reason is that the performance of such networks drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.Peer ReviewedPostprint (published version

Supporting Real-Time Communication in CSMA-Based Networks : the VTP-CSMA Virtual Token Passing Approach

Tese de doutoramento. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200