9,333 research outputs found

    DSN advanced receiver: Breadboard description and test results

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    A breadboard Advanced Receiver for use in the Deep Space Network was designed, built, and tested in the laboratory. Field testing was also performed during Voyager Uranus encounter at DSS-13. The development of the breadboard is intended to lead towards implementation of the new receiver throughout the network. The receiver is described on a functional level and then in terms of more specific hardware and software architecture. The results of performance tests in the laboratory and in the field are given. Finally, there is a discussion of suggested improvements for the next phase of development

    Built-in self test of high speed analog-to-digital converters

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    Signals found in nature need to be converted to the digital domain through analog-to-digital converters (ADCs) to be processed by digital means [1]. For applications in communication and measurement [2], [3], high conversion rates are required. With advances of the complementary metal oxide semiconductor (CMOS) technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT) and to collect and analyze their responses.publishe

    A built-in self-test technique for high speed analog-to-digital converters

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    Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

    An embedded tester core for mixed-signal System-on-Chip circuits

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    A four channel, self-calibrating, high resolution, time to digital converter

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    A four channel, self-calibrating, High Resolution Time to Digital Converter (HRTDC) with an RMS error of 35 ps over a dynamic range of 3.2 \mu s has been developed. Its architecture is based on an arr ay of delay locked loops and an 8-bit coarse time counter driven by an 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read- out FIFO. The HRTDC has been built in a 0.7 \mu m CMOS process using 23 mm^2 of silicon area

    An Analog Multiphase Self-Calibrating DLL to Minimize the Effects of Process, Supply Voltage, and Temperature Variations

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    Delay locked loops have been found to be useful tools in such applications as computing, TDCs, and communications. These system can be found in space exploration vehicles and satellites, which operate in extreme environments. Unfortunately, in these environments supply voltage and temperature will not be constant, therefore they must be under consideration when designing a DLL. Furthermore, solar radiation in conjunction with the varying environmental aspects, could cause the delay locked loop to lose it locked state. Delay locked loops are inherently good at tracking these environmental aspects, but in order to do so, the voltage controlled delay line must exhibit a very large gain, which translates to a large capture range. Assuming charged particles hit a key node in the DLL (e.g. the control voltage), the DLL would lose lock and would have to recapture it. Depending on the severity of the uctuation, this relocking process could easily take on the order of many microseconds assuming the bandwidth was kept low to minimize jitter. To date, no delay locked loops have been published for extreme environment applications. In many other extreme environment circuits, calibration techniques have been applied to minimize the environmental effects. Whereas there have been multiple calibration methods published related to delay locked loops, none of them were intended for extreme environments. Furthermore, none of these methods are directly suitable for an analog multiphase delay locked loop. The self-calibrating DLL in this work includes an all digital calibration circuit, as well as a system transient monitor. The coarse calibration helps minimize global process, voltage, and temperature errors for an analog multiphase DLL. The system monitor is used to detect any transients that might cause the DLL to unlock, which could be used to allow the DLL to be recalibrated to the new environmental conditions. The presented measurement results will demonstrate that the DLL can be used in extreme environments such as space, or other extreme environment applications

    Engineering evaluations and studies. Volume 3: Exhibit C

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    High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

    Investigation into synchronization for partial response signals and the development of a clock recovery scheme for 49QPRS signals

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    ThesisData communication is used increasingly in modern society. It is against this background that research is conducted worldwide toward the improvement of existing, as well as the development of new, improved communication techniques. Correlative encoding of data before transmission IS a very frequency-effective communication technique. The extent to which any communication technique is used, however, is dependent on a wide variety of factors. This study regarding the synchronisation of 49QPRS signals was undertaken with this in mind. Since digital signal processing (DSP) is used increasingly in modern communication systems, both a data transmitter and receiver were implemented by making use of this technique. Not only would this result in a system with all the desirable characteristics inherent to DSP, but, by making limited changes to the supporting software, the evaluation of a wide variety of alternatives became feasible. During the study a system making use of a pilot tone at one third the frequency of the carrier frequency was developed. The receiver recovers this signal by means of DSP techniques and its frequency is tripled. The phase of this recovered signal is crosscorrelated every 650 ~s in time with a locally generated signal of the correct frequency - and the phase of the locally generated signal is adjusted accordingly. It was found that the accuracy and stability of the locally generated signal were such that sufficient synchronisation was obtained in this manner. The quality of synchronisation is a function of the level of the pilot tone and if this tone should decrease to below a certain value, unacceptably large phase adjustments have to be made. This results in a senous degradation of the spectral purity of the recovered signal. However, the system as described exhibits extremely good noise immunity. During the development of the clock frequency recovery system, a baseband filter with a unique frequency response was defined. Making use of this, in conjunction with a limited amount of pre-processing, and an absolute value rectifier, recovery of the clock frequency becomes possible. In order to limit the amount of processing by the receiver, the baseband filter was implemented in its entirety in the transmitter. The recovered signal showed a moderate amount of amplitude variation, but an extremely stable synchronising signal could be derived from this. During the study both levels of synchronisation required by a hypothetical 49QPRS data communication system were therefore investigated fully and solutions found

    Survey of timing/synchronization of operating wideband digital communications networks

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    In order to benefit from experience gained from the synchronization of operational wideband digital networks, a survey was made of three such systems: Data Transmission Company, Western Union Telegraph Company, and the Computer Communications Group of the Trans-Canada Telephone System. The focus of the survey was on deployment and operational experience from a practical (as opposed to theoretical) viewpoint. The objective was to provide a report on the results of deployment how the systems performed, and wherein the performance differed from that predicted or intended in the design. It also attempted to determine how the various system designers would use the benefit of hindsight if they could design those same systems today
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