Energy management of Li-Po batteries in the mobile robotics domain

Mestrado de dupla diplomação com a Ecole Supérieure en Sciences Appliquées de TlemcenThe importance of energy storage continues to grow, whether in power generation, consumer electronics, aviation, or other systems. Therefore, energy management in batteries is becoming an increasingly crucial aspect of optimizing the overall system and must be done properly. Very few works have been found in the literature proposing the implementation of algorithms such as EKF to predict the SOC in small systems such as mobile robots, where computational power in some application is severely lacking. To this end, this work proposes an implementation of two algorithms mainly reported in the literature for SOC estimation, in an ATMEGA328P microcontroller-based BMS, this embedded system is designed taking into consideration the criteria already defined for such a system and adding the aspect of flexibility and ease of implementation. One of the implemented algorithms performs the prediction, while the other will be responsible for the monitoring.A importância do armazenamento de energia continua a crescer, seja na produção de energia, electrónica de consumo, aviação, ou outros sistemas. Por conseguinte, a gestão de energia em baterias está a tornar-se um aspecto cada vez mais crucial na optimização de todo o sistema e deve ser feita correctamente. Muito poucos trabalhos foram encontrados na literatura propondo a implementação de algoritmos como o EKF para prever o SOC em pequenos sistemas, tais como robôs móveis, onde a capacidade vezes é muitos aplicação escassa. Para este fim, este trabalho propõe uma implementação dos dois algoritmos principalmente relatados na literatura para a estimativa do SOC, num BMS baseado em microcontroladores ATMEGA328P, este sistema incorporado é concebido tendo em consideração os critérios já definidos para tal sistema e acrescentando o aspecto de flexibilidade e facilidade de implementação. Um dos algoritmos implementados realiza a previsão, enquanto que o outro será responsável pela monitorização

Advancements in Superconducting Microwave Cavities and Qubits for Quantum Information Systems

Superconducting microwave cavities with ultra-high Q-factors are revolutionizing the field of quantum computing, offering long coherence times exceeding 1 ms, which is critical for realizing scalable multi-qubit quantum systems with low error rates. In this work, we provide an in-depth analysis of recent advances in ultra-high Q-factor cavities, integration of Josephson junction-based qubits, and bosonic-encoded qubits in 3D cavities. We examine the sources of quantum state dephasing caused by damping and noise mechanisms in cavities and qubits, highlighting the critical challenges that need to be addressed to achieve even higher coherence times. We critically survey the latest progress made in implementing single 3D qubits using superconducting materials, normal metals, and multi-qubit and multi-state quantum systems. Our work sheds light on the promising future of this research area, including novel materials for cavities and qubits, modes with nontrivial topological properties, error correction techniques for bosonic qubits, and new light-matter interaction effects

Current-mode processing based Temperature-to-Digital Converters for MEMS applications

This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results.This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results

Clock multiplication techniques for high-speed I/Os

Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored. First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz. Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB. Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively

Feature Papers in Eng

This Special Issue is a collection of high-quality reviews and original papers from editorial board members, guest editors, and leading researchers discussing new knowledge or new cutting-edge developments in the field of engineering

A design-build-test-learn tool for synthetic biology

Modern synthetic gene regulatory networks emerge from iterative design-build-test cycles that encompass the decisions and actions necessary to design, build, and test target genetic systems. Historically, such cycles have been performed manually, with limited formal problem-definition and progress-tracking. In recent years, researchers have devoted substantial effort to define and automate many sub-problems of these cycles and create systems for data management and documentation that result in useful tools for solving portions of certain workflows. However, biologists generally must still manually transfer information between tools, a process that frequently results in information loss. Furthermore, since each tool applies to a different workflow, tools often will not fit together in a closed-loop and, typically, additional outstanding sub-problems still require manual solutions. This thesis describes an attempt to create a tool that harnesses many smaller tools to automate a fully closed-loop decision-making process to design, build, and test synthetic biology networks and use the outcomes to inform redesigns. This tool, called Phoenix, inputs a performance-constrained signal-temporal-logic (STL) equation and an abstract genetic-element structural description to specify a design and then returns iterative sets of building and testing instructions. The user executes the instructions and returns the data to Phoenix, which then processes it and uses it to parameterize models for simulation of the behavior of compositional designs. A model-checking algorithm then evaluates these simulations, and returns to the user a new set of instructions for building and testing the next set of constructs. In cases where experimental results disagree with simulations, Phoenix uses grammars to determine where likely points of design failure might have occurred and instructs the building and testing of an intermediate composition to test where failures occurred. A design tree represents the design hierarchy displayed in the user interface where progress can be tracked and electronic datasheets generated to review results. Users can validate the computations performed by Phoenix by using them to create sets of classic and novel temporal synthetic genetic regulatory functions in E. coli.2016-12-31T00:00:00

18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems: Proceedings

Proceedings of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems, which took place in Dresden, Germany, 26 – 28 May 2010.:Welcome Address ........................ Page I Table of Contents ........................ Page III Symposium Committees .............. Page IV Special Thanks ............................. Page V Conference program (incl. page numbers of papers) ................... Page VI Conference papers Invited talks ................................ Page 1 Regular Papers ........................... Page 14 Wednesday, May 26th, 2010 ......... Page 15 Thursday, May 27th, 2010 .......... Page 110 Friday, May 28th, 2010 ............... Page 210 Author index ............................... Page XII