22,570 research outputs found
Using ultra-thin parylene films as an organic gate insulator in nanowire field-effect transistors
We report the development of nanowire field-effect transistors featuring an
ultra-thin parylene film as a polymer gate insulator. The room temperature,
gas-phase deposition of parylene is an attractive alternative to oxide
insulators prepared at high temperatures using atomic layer deposition. We
discuss our custom-built parylene deposition system, which is designed for
reliable and controlled deposition of <100 nm thick parylene films on III-V
nanowires standing vertically on a growth substrate or horizontally on a device
substrate. The former case gives conformally-coated nanowires, which we used to
produce functional -gate and gate-all-around structures. These give
sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding at
room temperature. For the gate-all-around structure, we developed a novel
fabrication strategy that overcomes some of the limitations with previous
lateral wrap-gate nanowire transistors. Finally, we show that parylene can be
deposited over chemically-treated nanowire surfaces; a feature generally not
possible with oxides produced by atomic layer deposition due to the surface
`self-cleaning' effect. Our results highlight the potential for parylene as an
alternative ultra-thin insulator in nanoscale electronic devices more broadly,
with potential applications extending into nanobioelectronics due to parylene's
well-established biocompatible properties
Monte Carlo simulations of high-performance implant free In<sub>0.3</sub>Ga<sub>0.7</sub> nano-MOSFETs for low-power CMOS applications
No abstract available
DTMOS-Based 0.4V Ultra Low-Voltage Low-Power VDTA Design and Its Application to EEG Data Processing
In this paper, an ultra low-voltage, ultra low-power voltage differencing transconductance amplifier (VDTA) is proposed. DTMOS (Dynamic Threshold Voltage MOS) transistors are employed in the design to effectively use the ultra low supply voltage. The proposed VDTA is composed of two operational transconductance amplifiers operating in the subthreshold region. Using TSMC 0.18”m process technology parameters with symmetric ±0.2V supply voltage, the total power consumption of the VDTA block is found as just 5.96 nW when the transconductances have 3.3 kHz, 3 dB bandwidth. The proposed VDTA circuit is then used in a fourth-order double-tuned band-pass filter for processing real EEG data measurements. The filter achieves close to 64 dB dynamic range at 2% THD with a total power consumption of 12.7 nW
Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors
We introduce and experimentally validate a new macro-level model of the CPU
temperature/power relationship within nanometer-scale application processors or
system-on-chips. By adopting a holistic view, this model is able to take into
account many of the physical effects that occur within such systems. Together
with two algorithms described in the paper, our results can be used, for
instance by engineers designing power or thermal management units, to cancel
the temperature-induced bias on power measurements. This will help them gather
temperature-neutral power data while running multiple instance of their
benchmarks. Also power requirements and system failure rates can be decreased
by controlling the CPU's thermal behavior.
Even though it is usually assumed that the temperature/power relationship is
exponentially related, there is however a lack of publicly available physical
temperature/power measurements to back up this assumption, something our paper
corrects. Via measurements on two pertinent platforms sporting nanometer-scale
application processors, we show that the power/temperature relationship is
indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range.
Our data suggest that, for application processors operating between 20{\deg}C
and 50{\deg}C, a quadratic model is still accurate and a linear approximation
is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded
Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV
Organic film thickness influence on the bias stress instability in Sexithiophene Field Effect Transistors
In this paper, the dynamics of bias stress phenomenon in Sexithiophene (T6)
Field Effect Transistors (FETs) has been investigated. T6 FETs have been
fabricated by vacuum depositing films with thickness from 10 nm to 130 nm on
Si/SiO2 substrates. After the T6 film structural analysis by X-Ray diffraction
and the FET electrical investigation focused on carrier mobility evaluation,
bias stress instability parameters have been estimated and discussed in the
context of existing models. By increasing the film thickness, a clear
correlation between the stress parameters and the structural properties of the
organic layer has been highlighted. Conversely, the mobility values result
almost thickness independent
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