Transcribing Content from Structural Images with Spotlight Mechanism

Transcribing content from structural images, e.g., writing notes from music scores, is a challenging task as not only the content objects should be recognized, but the internal structure should also be preserved. Existing image recognition methods mainly work on images with simple content (e.g., text lines with characters), but are not capable to identify ones with more complex content (e.g., structured symbols), which often follow a fine-grained grammar. To this end, in this paper, we propose a hierarchical Spotlight Transcribing Network (STN) framework followed by a two-stage "where-to-what" solution. Specifically, we first decide "where-to-look" through a novel spotlight mechanism to focus on different areas of the original image following its structure. Then, we decide "what-to-write" by developing a GRU based network with the spotlight areas for transcribing the content accordingly. Moreover, we propose two implementations on the basis of STN, i.e., STNM and STNR, where the spotlight movement follows the Markov property and Recurrent modeling, respectively. We also design a reinforcement method to refine the framework by self-improving the spotlight mechanism. We conduct extensive experiments on many structural image datasets, where the results clearly demonstrate the effectiveness of STN framework.Comment: Accepted by KDD2018 Research Track. In proceedings of the 24th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining (KDD'18

The 1990 progress report and future plans

This document describes the progress and plans of the Artificial Intelligence Research Branch (RIA) at ARC in 1990. Activities span a range from basic scientific research to engineering development and to fielded NASA applications, particularly those applications that are enabled by basic research carried out at RIA. Work is conducted in-house and through collaborative partners in academia and industry. Our major focus is on a limited number of research themes with a dual commitment to technical excellence and proven applicability to NASA short, medium, and long-term problems. RIA acts as the Agency's lead organization for research aspects of artificial intelligence, working closely with a second research laboratory at JPL and AI applications groups at all NASA centers

Multilevel Power Estimation Of VLSI Circuits Using Efficient Algorithms

New and complex systems are being implemented using highly advanced Electronic Design Automation (EDA) tools. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. Now low power designs are not only used in small size applications like cell phones and handheld devices but also in high-performance computing applications. Embedded memories have been used extensively in modern SOC designs. In order to estimate the power consumption of the entire design correctly, an accurate memory power model is needed. However, the memory power model commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models are built with lookup tables. However, building the power models with lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. This thesis involves two parts. In first part it uses the Synopsys power measurement tools together with the use of synthesis and extraction tools to determine power consumed by various macros at different levels of abstraction including the Register Transfer Level (RTL), the gate and the transistor level. In general, it can be concluded that as the level of abstraction goes down the accuracy of power measurement increases depending on the tool used. In second part a novel power modeling approach for complex circuits by using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation has been developed. Our neural power model has very low complexity such that this power model can be used for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distributions. Unlike the power characterization process in traditional approaches, our characterization process is very simple and straightforward. More importantly, using the neural power model for power estimation does not require any transistor-level or gate-level description of the circuits. The experimental results have shown that the estimations are accurate and efficient for different test sequences with wide range of input distributions

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

A neural compiler

AbstractThis paper describes a neural compiler. The input of the compiler is a PASCAL Program. The compiler produces a neural network that computes what is specified by the PASCAL program. The compiler generates an intermediate code called cellular code