241 research outputs found

    Deep Space Network information system architecture study

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    The purpose of this article is to describe an architecture for the Deep Space Network (DSN) information system in the years 2000-2010 and to provide guidelines for its evolution during the 1990s. The study scope is defined to be from the front-end areas at the antennas to the end users (spacecraft teams, principal investigators, archival storage systems, and non-NASA partners). The architectural vision provides guidance for major DSN implementation efforts during the next decade. A strong motivation for the study is an expected dramatic improvement in information-systems technologies, such as the following: computer processing, automation technology (including knowledge-based systems), networking and data transport, software and hardware engineering, and human-interface technology. The proposed Ground Information System has the following major features: unified architecture from the front-end area to the end user; open-systems standards to achieve interoperability; DSN production of level 0 data; delivery of level 0 data from the Deep Space Communications Complex, if desired; dedicated telemetry processors for each receiver; security against unauthorized access and errors; and highly automated monitor and control

    The NASA SBIR product catalog

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    The purpose of this catalog is to assist small business firms in making the community aware of products emerging from their efforts in the Small Business Innovation Research (SBIR) program. It contains descriptions of some products that have advanced into Phase 3 and others that are identified as prospective products. Both lists of products in this catalog are based on information supplied by NASA SBIR contractors in responding to an invitation to be represented in this document. Generally, all products suggested by the small firms were included in order to meet the goals of information exchange for SBIR results. Of the 444 SBIR contractors NASA queried, 137 provided information on 219 products. The catalog presents the product information in the technology areas listed in the table of contents. Within each area, the products are listed in alphabetical order by product name and are given identifying numbers. Also included is an alphabetical listing of the companies that have products described. This listing cross-references the product list and provides information on the business activity of each firm. In addition, there are three indexes: one a list of firms by states, one that lists the products according to NASA Centers that managed the SBIR projects, and one that lists the products by the relevant Technical Topics utilized in NASA's annual program solicitation under which each SBIR project was selected

    Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

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    Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable

    A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O

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    This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-μm fully digital CMOS technology, contains ∼ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm2 and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 μs have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.European Commission IST-2001-38097Office of Naval Research (USA) N00014021088

    NASA Tech Briefs, November 2004

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    Topics include: Multifunction Imaging and Spectroscopic Instrument; Position-Finding Instrument Built Around a Magnetometer; Improved Measurement of Dispersion in an Optical Fiber; Probe for Sampling of Interstitial Fluid From Bone; Neuropsychological Testing of Astronauts; Method of Calibration for a Large Cathetometer System; Four-Channel PC/104 MIL-STD-1553 Circuit Board; Improved Method of Locating Defects in Wiring Insulation; Strobe Traffic Lights Warn of Approaching Emergency Vehicles; Improved Timing Scheme for Spaceborne Precipitation Radar; Concept for Multiple-Access Free-Space Laser Communications; Variable Shadow Screens for Imaging Optical Devices; Verifying Diagnostic Software; Initial Processing of Infrared Spectral Data; Activity-Centric Approach to Distributed Programming; Controlling Distributed Planning; New Material for Surface-Enhanced Raman Spectroscopy; Treated Carbon Nanofibers for Storing Energy in Aqueous KOH; Advanced Infant Car Seat Would Increase Highway Safety; Development of Biomorphic Flyers; Second-Generation Six-Limbed Experimental Robot; Miniature Linear Actuator for Small Spacecraft; Process for Making Single-Domain Magnetite Crystals; A New Process for Fabricating Random Silicon Nanotips; Resin-Transfer-Molding of a Tool Face; Improved Phase-Mask Fabrication of Fiber Bragg Gratings; Tool for Insertion of a Fiber-Optic Terminus in a Connector; Nanofluidic Size-Exclusion Chromatograph; Lightweight, Low-CTE Tubes Made From Biaxially Oriented LCPs; Using Redundancy To Reduce Errors in Magnetometer Readings; Compact Instrument for Measuring Profile of a Light Beam; Multilayer Dielectric Transmissive Optical Phase Modulator; Second-Generation Multi-Angle Imaging Spectroradiometer; Real-Time Adaptive Color Segmentation by Neural Networks; Research and Development in Optical Communications; Tests of Multibeam Scintillation Mitigation on Laser Uplinks; and Spaceborne Infrared Atmospheric Sounder

    Advanced photonic and electronic systems - WILGA 2017

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    WILGA annual symposium on advanced photonic and electronic systems has been organized by young scientist for young scientists since two decades. It traditionally gathers more than 350 young researchers and their tutors. Ph.D students and graduates present their recent achievements during well attended oral sessions. Wilga is a very good digest of Ph.D. works carried out at technical universities in electronics and photonics, as well as information sciences throughout Poland and some neighboring countries. Publishing patronage over Wilga keep Elektronika technical journal by SEP, IJET by PAN and Proceedings of SPIE. The latter world editorial series publishes annually more than 200 papers from Wilga. Wilga 2017 was the XL edition of this meeting. The following topical tracks were distinguished: photonics, electronics, information technologies and system research. The article is a digest of some chosen works presented during Wilga 2017 symposium. WILGA 2017 works were published in Proc. SPIE vol.10445

    Integrated polymer photonics : fabrication, design, characterization and applications

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    Campus Telecommunications Systems: Managing Change

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    The purpose of this book is to provide a broadbased understanding of the rapidly changing environment of campus telecommunications. The anticipated audience for this material is the non-technical university administrator who may not have direct responsibility for telecommunications, but has a need to understand the general environment in which his telecommunications manager functions and the basic concepts of the technology. Five topic areas were selected that best cover the preponderance of issues. No attempt has been made to associate or closely coordinate materials from one chapter\u27s subject to that of any other. Each chapter generally stands alone. In total, however, the five chapters address the topics and issues that most often generate inquiries from university administrators outside the telecommunications department. Introduction 1 The Changing Telecommunications Environment 2 Telecommunications Technology and the Campus 3 Student Services 4 Financing a New Telecommunications System . 5 Selecting a Consultant Glossary Inde

    Self-Evaluation Applied Mathematics 2003-2008 University of Twente

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    This report contains the self-study for the research assessment of the Department of Applied Mathematics (AM) of the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) at the University of Twente (UT). The report provides the information for the Research Assessment Committee for Applied Mathematics, dealing with mathematical sciences at the three universities of technology in the Netherlands. It describes the state of affairs pertaining to the period 1 January 2003 to 31 December 2008

    A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

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    The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.The research leading to these results has received funding from the Spanish Government and European FEDER funds (DPI2012-32390), the Valencia Regional Government (PROMETEO/2013/085) and the University of Alicante (GRE12-17)
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