Power-Aware Training for Energy-Efficient Printed Neuromorphic Circuits

There is an increasing demand for next-generation flexible electronics in emerging low-cost applications such as smart packaging and smart bandages, where conventional silicon electronics cannot enter due to cost and form factor. In these domains, ultra-low-cost, high flexibility, and customizability are required. In this regard, printed electronics emerge as a complementary solution offering the aforementioned properties. To respect the constraints in those application scenarios and equip printed devices with the fundamental capability to process information, analog printed neuromorphic circuits offer multiple advantages, including strong expressiveness, streamlined circuit primitives, and a highly efficient machine learning-based design process. In this work, we focus on designing low-power printed neuromorphic circuits at the algorithmic level. By developing accurate power models for the circuit primitives, the power consumption can be considered into the design process. Subsequently, Pareto analysis is employed to examine the relationship between accuracy and power consumption. Experimental results reveal that, with the proposed approach, 2× reduction of the power consumption can be realized while maintaining 95% of classification accuracy. This approach has significant implications for the future development of energy-efficient printed neuromorphic circuits and their potential applications in IoT and AI intersections

Soft eSkin:distributed touch sensing with harmonized energy and computing

Inspired by biology, significant advances have been made in the field of electronic skin (eSkin) or tactile skin. Many of these advances have come through mimicking the morphology of human skin and by distributing few touch sensors in an area. However, the complexity of human skin goes beyond mimicking few morphological features or using few sensors. For example, embedded computing (e.g. processing of tactile data at the point of contact) is centric to the human skin as some neuroscience studies show. Likewise, distributed cell or molecular energy is a key feature of human skin. The eSkin with such features, along with distributed and embedded sensors/electronics on soft substrates, is an interesting topic to explore. These features also make eSkin significantly different from conventional computing. For example, unlike conventional centralized computing enabled by miniaturized chips, the eSkin could be seen as a flexible and wearable large area computer with distributed sensors and harmonized energy. This paper discusses these advanced features in eSkin, particularly the distributed sensing harmoniously integrated with energy harvesters, storage devices and distributed computing to read and locally process the tactile sensory data. Rapid advances in neuromorphic hardware, flexible energy generation, energy-conscious electronics, flexible and printed electronics are also discussed. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’

Energy-Efficient In-Memory Architectures Leveraging Intrinsic Behaviors of Embedded MRAM Devices

For decades, innovations to surmount the processor versus memory gap and move beyond conventional von Neumann architectures continue to be sought and explored. Recent machine learning models still expend orders of magnitude more time and energy to access data in memory in addition to merely performing the computation itself. This phenomenon referred to as a memory-wall bottleneck, is addressed herein via a completely fresh perspective on logic and memory technology design. The specific solutions developed in this dissertation focus on utilizing intrinsic switching behaviors of embedded MRAM devices to design cross-layer and energy-efficient Compute-in-Memory (CiM) architectures, accelerate the computationally-intensive operations in various Artificial Neural Networks (ANNs), achieve higher density and reduce the power consumption as crucial requirements in future Internet of Things (IoT) devices. The first cross-layer platform developed herein is an Approximate Generative Adversarial Network (ApGAN) designed to accelerate the Generative Adversarial Networks from both algorithm and hardware implementation perspectives. In addition to binarizing the weights, further reduction in storage and computation resources is achieved by leveraging an in-memory addition scheme. Moreover, a memristor-based CiM accelerator for ApGAN is developed. The second design is a biologically-inspired memory architecture. The Short-Term Memory and Long-Term Memory features in biology are realized in hardware via a beyond-CMOS-based learning approach derived from the repeated input information and retrieval of the encoded data. The third cross-layer architecture is a programmable energy-efficient hardware implementation for Recurrent Neural Network with ultra-low power, area-efficient spin-based activation functions. A novel CiM architecture is proposed to leverage data-level parallelism during the evaluation phase. Specifically, we employ an MRAM-based Adjustable Probabilistic Activation Function (APAF) via a low-power tunable activation mechanism, providing adjustable accuracy levels to mimic ideal sigmoid and tanh thresholding along with a matching algorithm to regulate neuronal properties. Finally, the APAF design is utilized in the Long Short-Term Memory (LSTM) network to evaluate the network performance using binary and non-binary activation functions. The simulation results indicate up to 74.5 x 215; energy-efficiency, 35-fold speedup and ~11x area reduction compared with the similar baseline designs. These can form basis for future post-CMOS based non-Von Neumann architectures suitable for intermittently powered energy harvesting devices capable of pushing intelligence towards the edge of computing network

Gestión de jerarquías de memoria híbridas a nivel de sistema

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadoras y Automática y de Ku Leuven, Arenberg Doctoral School, Faculty of Engineering Science, leída el 11/05/2017.In electronics and computer science, the term ‘memory’ generally refers to devices that are used to store information that we use in various appliances ranging from our PCs to all hand-held devices, smart appliances etc. Primary/main memory is used for storage systems that function at a high speed (i.e. RAM). The primary memory is often associated with addressable semiconductor memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as primary memory but also other purposes in computers and other digital electronic devices. The secondary/auxiliary memory, in comparison provides program and data storage that is slower to access but offers larger capacity. Examples include external hard drives, portable flash drives, CDs, and DVDs. These devices and media must be either plugged in or inserted into a computer in order to be accessed by the system. Since secondary storage technology is not always connected to the computer, it is commonly used for backing up data. The term storage is often used to describe secondary memory. Secondary memory stores a large amount of data at lesser cost per byte than primary memory; this makes secondary storage about two orders of magnitude less expensive than primary storage. There are two main types of semiconductor memory: volatile and nonvolatile. Examples of non-volatile memory are ‘Flash’ memory (sometimes used as secondary, sometimes primary computer memory) and ROM/PROM/EPROM/EEPROM memory (used for firmware such as boot programs). Examples of volatile memory are primary memory (typically dynamic RAM, DRAM), and fast CPU cache memory (typically static RAM, SRAM, which is fast but energy-consuming and offer lower memory capacity per are a unit than DRAM). Non-volatile memory technologies in Si-based electronics date back to the 1990s. Flash memory is widely used in consumer electronic products such as cellphones and music players and NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. The rapid increase of leakage currents in Silicon CMOS transistors with scaling poses a big challenge for the integration of SRAM memories. There is also the case of susceptibility to read/write failure with low power schemes. As a result of this, over the past decade, there has been an extensive pooling of time, resources and effort towards developing emerging memory technologies like Resistive RAM (ReRAM/RRAM), STT-MRAM, Domain Wall Memory and Phase Change Memory(PRAM). Emerging non-volatile memory technologies promise new memories to store more data at less cost than the expensive-to build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. These new memory technologies combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the non-volatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. The research and information on these Non-Volatile Memory (NVM) technologies has matured over the last decade. These NVMs are now being explored thoroughly nowadays as viable replacements for conventional SRAM based memories even for the higher levels of the memory hierarchy. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional(3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years...En el campo de la informática, el término ‘memoria’ se refiere generalmente a dispositivos que son usados para almacenar información que posteriormente será usada en diversos dispositivos, desde computadoras personales (PC), móviles, dispositivos inteligentes, etc. La memoria principal del sistema se utiliza para almacenar los datos e instrucciones de los procesos que se encuentre en ejecución, por lo que se requiere que funcionen a alta velocidad (por ejemplo, DRAM). La memoria principal está implementada habitualmente mediante memorias semiconductoras direccionables, siendo DRAM y SRAM los principales exponentes. Por otro lado, la memoria auxiliar o secundaria proporciona almacenaje(para ficheros, por ejemplo); es más lenta pero ofrece una mayor capacidad. Ejemplos típicos de memoria secundaria son discos duros, memorias flash portables, CDs y DVDs. Debido a que estos dispositivos no necesitan estar conectados a la computadora de forma permanente, son muy utilizados para almacenar copias de seguridad. La memoria secundaria almacena una gran cantidad de datos aun coste menor por bit que la memoria principal, siendo habitualmente dos órdenes de magnitud más barata que la memoria primaria. Existen dos tipos de memorias de tipo semiconductor: volátiles y no volátiles. Ejemplos de memorias no volátiles son las memorias Flash (algunas veces usadas como memoria secundaria y otras veces como memoria principal) y memorias ROM/PROM/EPROM/EEPROM (usadas para firmware como programas de arranque). Ejemplos de memoria volátil son las memorias DRAM (RAM dinámica), actualmente la opción predominante a la hora de implementar la memoria principal, y las memorias SRAM (RAM estática) más rápida y costosa, utilizada para los diferentes niveles de cache. Las tecnologías de memorias no volátiles basadas en electrónica de silicio se remontan a la década de1990. Una variante de memoria de almacenaje por carga denominada como memoria Flash es mundialmente usada en productos electrónicos de consumo como telefonía móvil y reproductores de música mientras NAND Flash solid state disks(SSDs) están progresivamente desplazando a los dispositivos de disco duro como principal unidad de almacenamiento en computadoras portátiles, de escritorio e incluso en centros de datos. En la actualidad, hay varios factores que amenazan la actual predominancia de memorias semiconductoras basadas en cargas (capacitivas). Por un lado, se está alcanzando el límite de integración de las memorias Flash, lo que compromete su escalado en el medio plazo. Por otra parte, el fuerte incremento de las corrientes de fuga de los transistores de silicio CMOS actuales, supone un enorme desafío para la integración de memorias SRAM. Asimismo, estas memorias son cada vez más susceptibles a fallos de lectura/escritura en diseños de bajo consumo. Como resultado de estos problemas, que se agravan con cada nueva generación tecnológica, en los últimos años se han intensificado los esfuerzos para desarrollar nuevas tecnologías que reemplacen o al menos complementen a las actuales. Los transistores de efecto campo eléctrico ferroso (FeFET en sus siglas en inglés) se consideran una de las alternativas más prometedores para sustituir tanto a Flash (por su mayor densidad) como a DRAM (por su mayor velocidad), pero aún está en una fase muy inicial de su desarrollo. Hay otras tecnologías algo más maduras, en el ámbito de las memorias RAM resistivas, entre las que cabe destacar ReRAM (o RRAM), STT-RAM, Domain Wall Memory y Phase Change Memory (PRAM)...Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

Tailored electrical characteristics in multilayer metal-oxide-based-memristive devices

Auf Mehrlagen-Metalloxiden basierende memristive Bauelemente sind einer der vielversprechendsten Kandidaten für neuromorphes Computing. Allerdings stellen spezifische Anwendungen des neuromorphen Computings unterschiedliche Anforderungen an die memristiven Bauelemente. Eine ungelöste Herausforderung in der technologischen Entwicklung ist daher das maßgeschneiderte Design von memristiven Bauelementen für spezifische Anwendungen. Insbesondere die unterschiedlichen Materialien des Schichtstapels erschweren die Herstellungsprozesse aufgrund einer großen Anzahl von Parametern, wie z. B. der Stapelsequenzen und -dicken und der Qualität sowie der Eigenschaften der einzelnen Schichten. Daher sind systematische Untersuchungen der einzelnen Bauelementparameter besonders entscheidend. Darüber hinaus müssen sie mit einem tiefgreifenden Verständnis der zugrundeliegenden physikalischen Prozesse kombiniert werden, um die Lücke zwischen Materialdesign und elektrischen Eigenschaften der resultierenden memristiven Bauelemente zuschließen. Um memristive Bauelemente mit unterschiedlichen resistiven Schalteigenschaften zu erhalten, werden verschiedene Abfolgen und Kombinationen von drei Metalloxidschichten (TiOx, HfOx, und AlOx) hergestellt und untersucht. Zunächst werden einschichtige Oxidbauelemente untersucht, um Kandidaten für mehrschichtige Stapel zu identifizieren. Zweitens werden zweischichtige TiOx/HfOx Oxidbauelemente hergestellt. Anhand von systematischen Experimenten und statistischen Analysen wird gezeigt, dass die Stöchiometrie, die Dicke, und die Fläche des Bauelements die Betriebsspannungen, die Nichtlinearität beim resistiven Schalten und die Variabilität beeinflussen. Drittens werden TiOx/AlOx/HfOx-basierte Bauelemente hergestellt. Durch das Hinzufügen von AlOx in die zweischichtigen Oxidstapel weisen diese dreischichtigen Bauelemente optimale elektrische Eigenschaften für den Einsatz in neuromorpher Hardware auf, wie z. B. elektroformierungsfreies und strombegrenzungsloses Schalten sowie eine lange Lebensdauer. Die entwickelten memristiven Bauelemente werden in Systeme, wie Kreuzpunkt-Strukturen und Ein-Transistor-ein-Memristor-Konfigurationen integriert. Hier wird die Eignung für effizientes neuromorphes Computing bewertet. Außerdem werden Methoden zur stufenlosen analogen Einstellung des Widerstands der Bauelemente demonstriert. Diese Eigenschaft ermöglicht effiziente neuromorphe Rechenschemata. Diese umfassende Studie beleuchtet die Beziehung zwischen den Bauelementparametern und den elektrischen Eigenschaften von mehrschichtigen memristiven Bauelementen auf Metalloxidbasis. Auf dieser Grundlage werden maßgeschneiderte Methoden für spezifische neuromorphe Anwendungen entwickelt.Multilayer metal-oxide-based-memristive devices are one of the most promising candidates for neuromorphic computing. However, specific applications of neuromorphic computing call for different requirements for memristive devices. Therefore, an open challenge in technological development is the tailored design of memristive devices for specific applications. In particular, multilayer stacks complicate fabrication processes due to a large number of device parameters such as staking sequences and thicknesses, quality, and property of each layer. Therefore, systematic investigations of the individual device parameters are particularly decisive. Moreover, they need to be combined with a profound understanding of the underlying physical processes to bridge the gap between material design and electrical characteristics of the resulting memristive devices. To obtain memristive devices with different resistance switching characteristics, various sequences and combinations of three metal oxide layers (TiOx, HfOx, and AlOx) are fabricated and studied. First, single-layer oxide devices are investigated to find desirable multilayer stacks for memristive devices. Second, TiOx/HfOx-based bilayer oxide devices are fabricated. Via systematic experiments and statistical analysis, it is shown that the stoichiometry, thickness, and device area influence operating voltages, non-linearity in resistive switching, and variability. Third, TiOx/AlOx/HfOx-based devices are fabricated. By adding AlOx into the bilayer oxide stacks, these trilayer devices present favorable electrical features for use in neuromorphic hardware, such as electroforming-free and compliance-free switching as well as long retention. The developed memristive devices are integrated into systems such as crossbar structures and one-transistor-one-memristor configurations. Here, suitability for efficient neuromorphic computing is assessed. Also, methods to tune the device resistance gradually in an analog fashion are demonstrated. This feature allows for efficient neuromorphic computation. This comprehensive study highlights the relationship between device parameters and electrical properties of multilayer metal-oxide-based memristive devices. On this basis, tailoring methodologies are established for specific neuromorphic applications

Resistive switching devices with improved control of oxygen vacancies dynamics

L'abstract è presente nell'allegato / the abstract is in the attachmen