JTEC Panel report on electronic manufacturing and packaging in Japan

This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies

Development of Thermal Spreading Technology Nowadays

[[abstract]]Thermal spreading is a technology of decreasing the hot spot for electronic cooling and other high heat flux applications, and is characterized by high heat transfer, uniformity of heat removal. Vapor chamber is one of the Thermal spreading technologies which depend on two phase heat pipe technology. This paper provides an introduction to vapor chamber for electronic cooling, high power LEDs, multi heat sources, communication devices, and bio technology applications, reviews the development of thermal spreading technology nowadays, and summarizes the data regarding effects of vapor chamber inside thermal module, future applications, and suggestion. Some models of multi heat sources cooling were also presented.[[conferencetype]]國際[[conferencedate]]20091021~20091023[[iscallforpapers]]Y[[conferencelocation]]Taipei, Taiwa

Miniaturizing microvias for multi-chip modules

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 63-64).Electronics packaging is continually migrating toward denser packaging. This encompasses a push toward multilevel die, denser metallization, and smaller microvias. In this thesis we investigate the miniaturization of laser-drilled microvias in polyimide dielectric for chips-first multi-chip module (MCM) technology. The challenge is to produce increasingly smaller microvias and package more microvias into a given area without sacrificing electrical performance. Principally, this means a microvia must maintain certain minimum electrical resistance and mechanical adhesion to the conducting layers. The thesis encompasses the following research: 1. Investigating the state of the art in laser-drilled polyimide microvias. 2. Designing and fabricating test structures with microvias, in which the state of the art is pushed in microvia size and/or aspect ratio. 3. Measuring the contact resistances of laser-drilled microvias in a Kelvin structure configuration. 4. Developing finite element models of Kelvin structures to estimate the contact resistance of miniature microvias.The experimental results of this thesis prove that microvias with approximately 19 pm diameter and 10 mQ contact resistance can be reliably fabricated for chips-first MCM technology.by Paul Gerard Puskarich.M.Eng

Novel Multi-layer Wiring Build-up using Electrochemical Pattern Replication (ECPR)

Abstract This paper discloses a novel, high accuracy and low cost integration method based on an Electrochemcial Pattern Replication (ECPR) technology for multi-level stacking applications such as integrated passives, multi-level redistribution layers and top level IC interconnect structures. It is demonstrated how a first copper layer is coated with BCB (Bisbenzocyclobutene), which is planarized with CMP (Chemical Mechanical Polishing) to uncover the first layer, where after a second patterned copper layer is fabricated with ECPR. This approach shows the feasibility of fabricating highly accurate multi-level wiring layers and still avoiding the issues related to increasing topography, which are particularly severe for thick metal layers. In addition, the constraints for the dielectric material is significantly reduced, since it does not have to be photosensitive or planarizing, which in turn opens up for the use of alternative dielectric materials, which may have better electrical and physical properties, that have not been usable with the traditional multi-level fabrication methods. Introduction The integration of more and more complex functions such as wireless communication capabilities on chips or packages puts new demands on the manufacturing methods for top metal layers. High density interconnects and integrated passives require a combination of resolution, accuracy, thickness uniformity typically offered only by dual damascene processes. At the same time there is a need for thicker metal, high deposition rates and low cost per layer, which is typically offered only by through mask plating processes. These combined requirements are difficult to address by most existing methods of today. The increasing demand for further miniaturization and functionality for electronic systems, particularly for mobile and wireless applications, has been driving the trend of fabricating multi-layer wiring, such as integrated passives and redistribution layers for Wafer Level Packaging (WLP) applications Particular for above-IC integrated passives and Integrated passive devices (IPDs) there has been a trend of fabricating thicker metal (copper circuits) since it lowers the series resistance of the devices, which in turn results in better performance (e.g higher capacitance or inductance value per area

CFD analysis of electronics chip cooling

Since the development of the first electronic digital computers in the 1940s, the effective removal of heat has played a key role in ensuring the reliable operation of successive generations of computers. As day by day the size of the electronic instruments decreases drastically and simultaneously the number of functions per chip increases hugely. So it’s a great challenge to packaging engineers to remove the heat generated by the chip efficiently. Many researches are going on in this direction for the past few decades. In the last decade or so CFD simulations have become more and more widely used in studies of electronic cooling. Validation of these simulations has been considered to be very important. In this study we are analyzing the cooling effects of the chip by modeling the geometry numerically. We have considered a single chip module. The modeling is carried out by solving the governing equations for a flow through a channel via obstruction. The case we have considered is transient laminar flow. The method we have used here to discretize the governing equations, namely the continuity equation, the momentum equation and the energy equation is Finite Difference Method (FDM). To solve the problem the algorithm we have used is Marker and Cell (MAC) method, and to discretize the convective term we have used the weighted second upwind and space centered difference. The diffusive terms are discretized by central difference scheme. The entire algorithm was written in FORTRAN-90. The geometry and the boundary conditions we have considered is for general applicability, that’s why we have non-dimensionalized the variables. In the discretization we have considered equal increment in both x-direction and y- direction. We have considered the domain 198 nodes in x-direction and 32 in y-direction. The case we are considering is constant temperature conditions. The temperature of the wall and that of the chip were considered to be unity and that of the inlet velocity temperature is considered to be zero. So the entire temperature range falls in between zero and one. The obstruction size we have considered are 3x3, 7x7, 11x11, and 15x 15, that means the blockage ratio nearly varies from 0.1 to 0.5. All the above cases are considered by varying the Reynolds number as 300, 600, 900, and 1200 that means all are in the laminar zone. After conducting the simulations we found the results, and by using different software packages like Surfer-32, Origin 6.1, and Grapher 1.09, we have plotted different contours of pressure and temperature, velocity profiles and variation of Nusselt number. Finally the outputs or graph and contours are analyzed for the process. In appendix-A, we have presented the output of FLUENT, which is simulated with same boundary conditions. So the results can be compared with it

LASER Tech Briefs, Spring 1994

Topics in this Laser Tech Brief include: Electronic Components and Circuits. Electronic Systems, Physical Sciences, Materials, Mechanics, Fabrication Technology, and books and reports

Prognostics and Health Management of Electronics by Utilizing Environmental and Usage Loads

Prognostics and health management (PHM) is a method that permits the reliability of a system to be evaluated in its actual application conditions. Thus by determining the advent of failure, procedures can be developed to mitigate, manage and maintain the system. Since, electronic systems control most systems today and their reliability is usually critical for system reliability, PHM techniques are needed for electronics. To enable prognostics, a methodology was developed to extract load-parameters required for damage assessment from irregular time-load data. As a part of the methodology an algorithm that extracts cyclic range and means, ramp-rates, dwell-times, dwell-loads and correlation between load parameters was developed. The algorithm enables significant reduction of the time-load data without compromising features that are essential for damage estimation. The load-parameters are stored in bins with a-priori calculated (optimal) bin-width. The binned data is then used with Gaussian kernel function for density estimation of the load-parameter for use in damage assessment and prognostics. The method was shown to accurately extract the desired load-parameters and enable condensed storage of load histories, thus improving resource efficiency of the sensor nodes. An approach was developed to assess the impact of uncertainties in measurement, model-input, and damage-models on prognostics. The approach utilizes sensitivity analysis to identify the dominant input variables that influence the model-output, and uses the distribution of measured load-parameters and input variables in a Monte-Carlo simulation to provide a distribution of accumulated damage. Using regression analysis of the accumulated damage distributions, the remaining life is then predicted with confidence intervals. The proposed method was demonstrated using an experimental setup for predicting interconnect failures on electronic board subjected to field conditions. A failure precursor based approach was developed for remaining life prognostics by analyzing resistance data in conjunction with usage temperature loads. Using the data from the PHM experiment, a model was developed to estimate the resistance based on measured temperature values. The difference between actual and estimated resistance value in time-domain were analyzed to predict the onset and progress of interconnect degradation. Remaining life was predicted by trending several features including mean-peaks, kurtosis, and 95% cumulative-values of the resistance-drift distributions

NASA SBIR abstracts of 1992, phase 1 projects

The objectives of 346 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1992 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 346, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1992 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

NASA Tech Briefs, December 1999

Topics include: Imaging/Videos/Cameras; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Books and Reports