Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algorithms that are used to implement the baseband processing and the channel decoding. Efficient implementation of multiple wireless standards in mobile terminals requires energy-efficient and flexible hardware. We propose to implement both the baseband processing and channel decoding in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains many processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. We already showed the feasibility to implement the baseband processing of OFDM and WCDMA based communication systems in the MONTIUM. In this paper we implemented two kinds of channel decoders in the same MONTIUM architecture: Viterbi and Turbo decoding

Implementation of Multi-standard Wireless Communication Receivers in a Heterogeneous Reconfigurable System-on-Chip

Future mobile terminals become multi-mode communication systems. In order to handle different standards, we propose to perform baseband processing in heterogeneous reconfigurable hardware. Not only the baseband processing but also error decoding differs for every communication system. We already proposed implementations of the baseband processing part of an OFDM receiver and a Wideband CDMA receiver in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. Now, we also implemented an adaptive Viterbi decoder in the same coarse-grained MONTIUM architecture. The rate, constraint length and decision depth of the decoder can be adjusted to different communication systems. We show that the flexibility in the coarse-grained reconfigurable architecture is more than 200 times as energy-efficient compared to a general purpose solution but only 24 times less efficient compared to a dedicated solution

A Reconfigurable Outer Modem Platform for Future Communications Systems

Future mobile and wireless communications networks require flexible modem architectures with high performance. Efficient utilization of application specific flexibility is key to fulfill these requirements. For high throughput a single processor can not provide the necessary computational power. Hence multi-processor architectures become necessary. This paper presents a multi-processor platform based on a new dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel decoding. Inherently parallel decoding tasks can be mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by a Network-on-Chip (NoC) such that the throughput of each node is not degraded. The dr-ASIP features Viterbi and Log-MAP decoding for support of convolutional and turbo codes of more than 10 currently specified mobile and wireless standards. Furthermore, its flexibility allows for adaptation to future systems

A common operator for FFT and FEC decoding

International audienceIn the Software Radio context, the parametrization is becoming an important topic especially when it comes to multistandard designs. This paper capitalizes on the Common Operator technique to present new common structures for the FFT and FEC decoding algorithms. A key benefit of exhibiting common operators is the regular architecture it brings when implemented in a Common Operator Bank (COB). This regularity makes the architecture open to future function mapping and adapted to accommodated silicon technology variability through dependable design