High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

© Allerton Press, Inc. 2018A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.Peer reviewe

A Silicon Carbide Power Management Solution for High Temperature Applications

The increasing demand for discrete power devices capable of operating in high temperature and high voltage applications has spurred on the research of semiconductor materials with the potential of breaking through the limitations of traditional silicon. Gallium nitride (GaN) and silicon carbide (SiC), both of which are wide bandgap materials, have garnered the attention of researchers and gradually gained market share. Although these wide bandgap power devices enable more ambitious commercial applications compared to their silicon-based counterparts, reaching their potential is contingent upon developing integrated circuits (ICs) capable of operating in similar environments. The foundation of any electrical system is the ability to efficiently condition and supply power. The work presented in this thesis explores integrated SiC power management solutions in the form of linear regulators and switched capacitor converters. While switched-mode converters provide high efficiency, the requirement of an inductor hinders the development of a compact, integrated solution that can endure harsh operating environments. Although the primary research motivation for wide bandgap ICs has been to provide control and protection circuitry for power devices, the circuitry designed in this work can be incorporated in stand-alone applications as well. Battery or generator powered data acquisition systems targeted towards monitoring industrial machinery is one potential usage scenario

Monolithic Integration of CMOS Charge Pumps for High Voltage Generation beyond 100 V

Monolithic integration of step-up DC-DC converters used to be one of the largest challenges in high voltage CMOS SoCs. Charge pumps are considered as the most promising solution regarding in- tegration levels compared to boost converter with bulky inductors. However, conventional charge pump architectures usually show significant drawbacks and reliability problems, when used as on- chip high voltage generators. Hence, innovative charge pump architectures are required to realize the monolithic integration of charge pumps in high voltage applications. In this dissertation, three 4-phase charge pump architectures with the dynamic body biasing tech- nique and clock schemes with dead time techniques were proposed to overcome drawbacks such as body effect and reverse current problem of traditional Pelliconi charge pump. The influences of high voltage CMOS sandwich capacitors on the voltage gain and power efficiency of charge pumps were extensively investigated. The most reasonable 4-phase charge pump architecture with a suitable configuration of high voltage sandwich capacitors regarding the voltage gain and power efficiency was chosen to implement two high voltage ASICs in an advanced 120 V 0.35 μm high voltage CMOS technology. The first test chip operates successfully and is able to generate up to 120 V from a 3.7 V low voltage DC supply, which shows the highest output voltage among all the reported fully integrated CMOS charge pumps. The measurement results confirmed the benefits of the proposed charge pump architectures and clock schemes. The second chip providing a similar output voltage has a reduced chip size mainly due to decreased capacitor areas by increased clock frequencies. Fur- thermore, the second chip with an on-chip clock generator works independently of external clock signals which shows the feasibility of integrated charge pumps as part of high voltage SoCs. Based on the successful implementation of those high voltage CMOS ASICs, further discussions on the stability of the output voltage, levels of integration and limitations in the negative high voltage generation of high voltage CMOS charge pumps are held with the aid of simulation or measurement results. Feed- back regulation by adjusting the clock frequency or DC power supply is able to stabilize the voltage performance effectively while being easily integrated on-chip. Increasing the clock frequency can significantly reduce the required capacitor values which results in reduced chip sizes. An application example demonstrates the importance of fully integrated high voltage charge pumps. Besides, a new design methodology for the on-chip high voltage generation using CMOS technolo- gies was proposed. It contains a general design flow focusing mainly on the feasibility and reliability of high voltage CMOS ASICs and design techniques for on-chip high voltage generators. In this dissertation, it is proven that CMOS charge pumps using suitable architectures regarding the required chip size and circuit reliability are able to be used as on-chip high voltage generators for voltages beyond 100 V . Several methods to improve the circuit performance and to extend the functionalities of high voltage charge pumps are suggested for future works

Analog Front End for RF Energy Harvesting

This thesis proposes a design for ultra low power sensitive single and dual band RF energy harvesting system for UHF microwave frequencies at 2.4-GHz and 865-MHz to 960- MHz(ISM band). The system is designed to power a load and generate a constant 1-V output voltage for a battery-less passive energy harvesting circuit. Input power is fed from 50 RF source to emulate antenna at UHF microwave band. The design includes single band and dual band off-chip RF matching circuit, RF limiter, Differential Rectifier, Power On Reset (POR), Band Gap Reference (BGR) and Low Drop Out Regulator (LDO). The number of rectifier stages is optimized to obtain a better efficiency to generate 1V output voltage. The full system performance has been verified by simulations for equivalent received power from -20-dBm to -10-dBm. The overall RF energy harvesting system efficiency at -14-dBm (10 m Distance from 4W EIRP source) input power for single band matching at 2.4-GHz is 46.9% with 54Kohm load and for dual band matching at 953-MHz and 2.4-GHz we achieve an efficiency of 41.5% with 61K ohm load and 46% with load 54.4Kohm respectively. The technology node employed is 0.18_m technology. The simulations are carried out at schematic level with bond wire parasitic’s and verified by post layout simulation. At the last we conclude by proposing a novel architecture for constant voltage battery charging

An adiabatic charge pump based charge recycling design style

A typical CMOS gate draws charge equal to C[subscript L]Vdd2 from the power supply (Vdd) where C[subscript L] is the load capacitance. Half of the energy is dissipated in the pull-up p-type network, and the other half is dissipated in the pull-down n-type network. Adiabatic CMOS circuit reduces the dissipated energy by providing the charge at a rate significantly lower than the inherent RC delay of the gate. The charge can also be recovered with an RLC oscillator based power supply. However, the two main problems with adiabatic design style are the design of a high frequency RLC oscillator for the power supply, and the need to slow down the rate of charge supply for lower energy. This reduction in speed of operation renders this adiabatic technique inapplicable in certain situations. A new approach incorporating an adiabatic charge pump that moves the slower adiabatic components away from the critical path of the logic is proposed in this work. The adiabatic delays of a charge pump are overlapped with the computing path logic delays. Hence, the proposed charge pump based recycling technique is especially effective for pipelined datapath computations (digital signal processing, DSP, is such a domain) where timing considerations are important. Also the proposed design style does not interfere with the critical path of the system, and hence the delay introduced by this scheme does not reduce the overall computational speed. In this work, we propose one implementation schema that involves tapping the ground-bound charge in a capacitor (virtual ground) and using an adiabatic charge-pump circuit to feed internal virtual power supplies. As the design relies on leakage charge to generate virtual power supplies, it is most effective in large circuits that undergo considerable switching activity resulting in substantial charge tapping by the proposed scheme. The proposed method has been implemented in DSP applications like FIR filter, DCT/IDCT filters and FFT filters. Simulations results in SPICE indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% with no loss in performance, paving way for a new approach towards conserving energy in complex digital systems