Communication‐less Synchronous Rectification for In Motion Wireless Charging

This thesis puts forward a control scheme to allow for synchronous rectification for dynamic wireless power transfer. The automotive industry is transitioning away from internal combustion engines (ICEs) and towards electric vehicles (EVs). This transition is spurred by the environmental and economic benefits EVs offer over ICEs. However, further improvements can still be made to how electric vehicles operate. One of these improvements is the technology of in motion wireless charging or dynamic wireless power transfer. In motion wireless charging offers the ability to remove existing range anxiety concerns for EVs. It also offers the potential for a reduction in battery sizes for EVs, which are the primary cost of EVs, this in turn decreases the total costs of mass EV adoption. Traditional implementations of in motion wireless charging utilize passive rectification to simplify controls between embedded primary pads and the vehicle. However, this solution while effective, limits the potential benefits of wireless charging. The use of synchronous or active rectification techniques, offer improved performance, control techniques, and bidirectional capabilities. However, the reason synchronous rectification is not already used in in motion charging is the complexity of synchronization over wireless communication. To move past this challenge, this thesis investigates a synchronization scheme that can be achieved without communication by taking advantage of induced free resonant currents in the vehicle’s tuning network to synchronize the switching transitions to receive power. In this thesis a traditional in motion wireless charging system utilizing passive rectification is designed and built as a benchmark for dynamic charging. Simulations of this control scheme are presented. Practical considerations are addressed for hardware realization. Finally, the control approach is validated through hardware in static and dynamic applications

Power Electronics Applications in Renewable Energy Systems

The renewable generation system is currently experiencing rapid growth in various power grids. The stability and dynamic response issues of power grids are receiving attention due to the increase in power electronics-based renewable energy. The main focus of this Special Issue is to provide solutions for power system planning and operation. Power electronics-based devices can offer new ancillary services to several industrial sectors. In order to fully include the capability of power conversion systems in the network integration of renewable generators, several studies should be carried out, including detailed studies of switching circuits, and comprehensive operating strategies for numerous devices, consisting of large-scale renewable generation clusters

DESIGN OF A MACHINE VISION CAMERA FOR SPATIAL AUGMENTED REALITY

Structured Light Imaging (SLI) is a means of digital reconstruction, or Three-Dimensional (3D) scanning, and has uses that span many disciplines. A projector, camera and Personal Computer (PC) are required to perform such 3D scans. Slight variances in synchronization between these three devices can cause malfunctions in the process due to the limitations of PC graphics processors as real-time systems. Previous work used a Field Programmable Gate Array (FPGA) to both drive the projector and trigger the camera, eliminating these timing issues, but still needing an external camera. This thesis proposes the incorporation of the camera with the FPGA SLI controller by means of a custom printed circuit board (PCB) design. Featuring a high speed image sensor as well as High Definition Multimedia Interface (HDMI) input and output, this PCB enables the FPGA to perform SLI scans as well as pass through HDMI video to the projector for Spatial Augmented Reality (SAR) purposes. Minimizing ripple noise on the power supply by means of effective circuit design and PCB layout, realizes a compact and cost effective machine vision sensing solution

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

Microchip test environment

With the ever-increasing demand for more powerful chips, it is necessary to integrate multiple circuits inside a chip. These chips are called a system on a chip (SoC). Even though SoCs integrate more and more functionality inside a single chip they still require a printed circuit board which at least provides power and input and output connectors. Tampere University together with multiple companies started SoC Hub project. The goal of this project is to develop a system on a chip and increase Finnish system on a chip design expertise. The target is to develop one system on a chip in a year with three SoCs in total. The goal of this master’s thesis is to design a printed circuit board that can be used to test the first iteration of the SoC. Printed circuit boards which are designed for testing have three main functions: provide power, provide input and output connectors and their circuitry, and to make testing as easy as possible. This system on a chip requires three different power rails, which must be turned on and off in a sequence and they must also be monitored in case of a fault. For this purpose, a power management system was developed in which a microcontroller monitors and controls the power rails. On the printed circuit board most of the input and output connectors use pin headers. The pin headers make testing easy as most signals are available in simple pin headers. Some signals also have more specialized connectors such as an SD card socket. Testability was also a major concern when deciding the stack up of the printed circuit board. All signals are routed on the outer layers so that they are easily available and can be slightly modified if needed. Some difficulties were also faced during the design process of the printed circuit board. Of these the biggest was the global chip shortage, because of which most of the chips that could have been used were not available. Due to chip shortage most of the chips had to be changed during the design phase and some chips had to be replaced by alternative means like using ready-made modules. Despite these problems the printed circuit boards were designed and manufactured before the SoCs arrived. The printed circuit boards were tested to be functional after which they could be used for their intended purpose of testing the SoCs

45-nm SOI CMOS Bluetooth Electrochemical Sensor for Continuous Glucose Monitoring

Due to increasing rates of diabetes, non-invasive glucose monitoring systems will become critical to improving health outcomes for an increasing patient population. Bluetooth integration for such a system has been previously unattainable due to the prohibitive energy consumption. However, enabling Bluetooth allows for widespread adoption due to the ubiquity of Bluetooth-enabled mobile devices. The objective of this thesis is to demonstrate the feasibility of a Bluetooth-based energy-harvesting glucose sensor for contact-lens integration using 45~nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The proposed glucose monitoring system includes a Bluetooth transmitter implemented as a two-point closed loop PLL modulator, a sensor potentiostat, and a 1st-order incremental delta-sigma analog-to-digital converter (IADC). This work details the complete system design including derivation of top-level specifications such as glucose sensing range, Bluetooth protocol timing, energy consumption, and circuit specifications such as carrier frequency range, output power, phase-noise performance, stability, resolution, signal-to-noise ratio, and power consumption. Three test chips were designed to prototype the system, and two of these were experimentally verified. Chip 1 includes a partial implementation of a phase-locked-loop (PLL) which includes a voltage-controlled-oscillator (VCO), frequency divider, and phase-frequency detector (PFD). Chip 2 includes the design of the sensor potentiostat and IADC. Finally, Chip 3 combines the circuitry of Chip 1 and Chip 2, along with a charge-pump, loop-filter and power amplifier to complete the system. Chip 1 DC power consumption was measured to be 204.8~$\mu$W, while oscillating at 2.441 GHz with an output power $P_{out}$ of -35.8 dBm, phase noise at 1 MHz offset $L(1\text{ MHz})$ of -108.5 dBc/Hz, and an oscillator figure of merit (FOM) of 183.44dB. Chip 2 achieves a total DC power consumption of 5.75~$\mu$W. The system has a dynamic range of 0.15~nA -- 100~nA at 10-bit resolution. The integral non-linearity (INL) and differential non-linearity (DNL) of the IADC were measured to be -6~LSB/$\pm$0.3~LSB respectively with a conversion time of 65.56~ms. This work achieves the best duty-cycled DC power consumption compared to similar glucose monitoring systems, while providing sufficient performance and range using Bluetooth