10,004 research outputs found
Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units
Tensor processing units (TPUs), specialized hardware accelerators for machine
learning tasks, have shown significant performance improvements when executing
convolutional layers in convolutional neural networks (CNNs). However, they
struggle to maintain the same efficiency in fully connected (FC) layers,
leading to suboptimal hardware utilization. In-memory analog computing (IMAC)
architectures, on the other hand, have demonstrated notable speedup in
executing FC layers. This paper introduces a novel, heterogeneous,
mixed-signal, and mixed-precision architecture that integrates an IMAC unit
with an edge TPU to enhance mobile CNN performance. To leverage the strengths
of TPUs for convolutional layers and IMAC circuits for dense layers, we propose
a unified learning algorithm that incorporates mixed-precision training
techniques to mitigate potential accuracy drops when deploying models on the
TPU-IMAC architecture. The simulations demonstrate that the TPU-IMAC
configuration achieves up to performance improvements, and
memory reductions compared to conventional TPU architectures for various CNN
models while maintaining comparable accuracy. The TPU-IMAC architecture shows
potential for various applications where energy efficiency and high performance
are essential, such as edge computing and real-time processing in mobile
devices. The unified training algorithm and the integration of IMAC and TPU
architectures contribute to the potential impact of this research on the
broader machine learning landscape
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
Binary Neural Networks (BNNs) are promising to deliver accuracy comparable to
conventional deep neural networks at a fraction of the cost in terms of memory
and energy. In this paper, we introduce the XNOR Neural Engine (XNE), a fully
digital configurable hardware accelerator IP for BNNs, integrated within a
microcontroller unit (MCU) equipped with an autonomous I/O subsystem and hybrid
SRAM / standard cell memory. The XNE is able to fully compute convolutional and
dense layers in autonomy or in cooperation with the core in the MCU to realize
more complex behaviors. We show post-synthesis results in 65nm and 22nm
technology for the XNE IP and post-layout results in 22nm for the full MCU
indicating that this system can drop the energy cost per binary operation to
21.6fJ per operation at 0.4V, and at the same time is flexible and performant
enough to execute state-of-the-art BNN topologies such as ResNet-34 in less
than 2.2mJ per frame at 8.9 fps.Comment: 11 pages, 8 figures, 2 tables, 3 listings. Accepted for presentation
at CODES'18 and for publication in IEEE Transactions on Computer-Aided Design
of Circuits and Systems (TCAD) as part of the ESWEEK-TCAD special issu
Depth from Monocular Images using a Semi-Parallel Deep Neural Network (SPDNN) Hybrid Architecture
Deep neural networks are applied to a wide range of problems in recent years.
In this work, Convolutional Neural Network (CNN) is applied to the problem of
determining the depth from a single camera image (monocular depth). Eight
different networks are designed to perform depth estimation, each of them
suitable for a feature level. Networks with different pooling sizes determine
different feature levels. After designing a set of networks, these models may
be combined into a single network topology using graph optimization techniques.
This "Semi Parallel Deep Neural Network (SPDNN)" eliminates duplicated common
network layers, and can be further optimized by retraining to achieve an
improved model compared to the individual topologies. In this study, four SPDNN
models are trained and have been evaluated at 2 stages on the KITTI dataset.
The ground truth images in the first part of the experiment are provided by the
benchmark, and for the second part, the ground truth images are the depth map
results from applying a state-of-the-art stereo matching method. The results of
this evaluation demonstrate that using post-processing techniques to refine the
target of the network increases the accuracy of depth estimation on individual
mono images. The second evaluation shows that using segmentation data alongside
the original data as the input can improve the depth estimation results to a
point where performance is comparable with stereo depth estimation. The
computational time is also discussed in this study.Comment: 44 pages, 25 figure
- …