KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters

The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams. However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency. In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary. In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed. Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 $\mu m$ SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 2$\times$2 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature. In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class $F^{-1}$ power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm. Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas

Nouvelles Topologies des diviseurs de puissance, balun et déphaseurs en bandes RF et millimétiques, apport des lignes à ondes lentes

L objectif de cette thèse a été premièrement de réaliser des dispositifs passifs intégrés à base de lignes à onde lentes nommées S-CPW (pour Slow-wave CoPlanar Waveguide ) aux fréquences millimétriques. Plusieurs technologies CMOS ou BiCMOS ont été utilisées: CMOS 65 nm et 28 nm ainsi que BiCMOS 55 nm. Deux baluns, le premier basé sur une topologie de rat-race et le second basé sur un diviseur de puissance de Wilkinson modifié, ainsi qu un inverseur de phase, ont été réalisés et mesurés dans la technologie CMOS 65 nm. Les résultats expérimentaux obtenus se situent à l état de l art en termes de performances électriques. Un coupler hybride et un diviseur de puissance avec des sorties en phase sans isolation ont été conçus en technologie CMOS 28 nm. Les simulations montrent de très bonnes performances pour des dispositifs compacts. Les circuits sont en cours de fabrication et pourront très bientôt être caractérisés. Ensuite, une nouvelle topologie de diviseurs de puissance, avec sorties en phase et isolé a été développée, offrant une grande flexibilité et compacité en comparaison des diviseurs de puissance traditionnels. Cette topologie est parfaitement adaptée pour les technologies silicium. Comme preuve de concept, deux diviseurs de puissance avec des caractéristiques différentes ont été réalisés en technologie PCB microruban à la fréquence de 2.45 GHz. Un composent a été conçu à 60 GHz en technologie BiCMOS 55 nm utilisant des lignes S CPW. Les simulations prouvent que le dispositif est faibles pertes, adapté et isolé. Les circuits sont également en cours de fabrication. Enfin, deux topologies de reflection type phase shifter ont été développées, la première dans la bande RF et la seconde aux fréquences millimétrique. Pour la bande RF, le déphasage atteint plus de 360 avec une figure de mérite très élevée en comparaison avec l état de l art. En ce qui concerne le déphaseur dans la bande millimétrique, la simulation montre un déphasage de 341 avec également une figure de mérite élevée.The first purpose of this work was the use of slow-wave coplanar waveguides (S CPW) to achieve various passive components with the aim to show their great potential and interest at millimetre-waves. Several CMOS or BiCMOS technologies were used: CMOS 65 nm and 28 nm, and BiCMOS 55 nm. Two baluns, one based on a rat-race topology and the other based on a modified Wilkinson power divider, and a phase inverter, were achieved and measured in a 65 nm CMOS technology. State-of-the-art results were achieved. A branch-line coupler and an in phase power divider without isolation were designed in a 28 nm CMOS technology. Really good performances are expected for these compact devices being yet under fabrication. Then, a new topology of in phase and isolated power divider was developed, leading to more flexibility and compactness, well suited to millimetre-wave frequencies. Two power dividers with different characteristics were realized in a PCB technology at 2.45 GHz by using microstrip lines, as a proof-of-concept. After that, a power divider was designed at the working frequency of 60 GHz in the 55 nm BiCMOS technology with S CPWs. The simulation results showed a low loss, full-matched and isolated component, which is also under fabrication and will be characterized as soon as possible. Finally, two new topologies of reflection type phase shifters were presented, one for the RF band and one for the millimetre-wave one. For the one in RF band, the phase shift can reach more than 360 with a great figure-of-merit as compared to the state-of-the-art. Concerning the phase shifter in the millimetre-wave band, the simulation results show a phase shift of 341 with also a high figure-of-merit.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

High Frequency Receiver Front-End Module for Active Antenna Applications

This research is based on the analysis and development of an integrated receiver front-end module for high gain active antenna systems at the K-band (20GHz). In the design of conventional satellite receivers (such as reflector antennas), the system is usually specified by the gain/directivity, gain-to-temperature ratio (G/T) and radiation pattern requirements. The challenge in high gain active antenna systems development, in addition to beam-forming/beam-steering requirements, is to develop transmit/receive modules which will meet the power, noise and radiation pattern requirements of the conventional antenna. In order to guarantee an optimal design, it is important to be able to translate the specifications from the system level to the transistor level. The focus is on the development of a single-channel CMOS-based integrated receiver module. The G/T requirement is analysed to derive the noise figure and gain specifications for the low noise amplifier(LNA). An LNA design in 65nm CMOS is demonstrated to achieve a 2.6dB noise figure and uses only 7mW of DC power. The digital phased shifter specifications are studied. The generation of "quantization lobes" is analysed and used to estimate the number of bits based on side-lobe level requirements. The design of a 5-bit digital phase shifter based on quadrature signal modulation and a unique digital control logic is presented and tested at 20GHz. The phase shifter is shown to achieve 10dB input and output return loss between 16-21GHz. The effect of pattern tapering on the side-lobe level is investigated and used to specify the minimum dynamic range for a variable gain amplifier (VGA). A VGA design is demonstrated to meet this dynamic range with low phase-frequency variation. A schematic level design of the proposed single-channel array is studied featuring a hybrid coupler and switch for polarisation requirements, as well as a low-voltage bandgap reference circuit. Simulations results verify that the receiver can be used to generate two hands of polarisation (right and left) with <1.1dB axial ratio

Radio Frequency and Millimeter Wave Circuit Component Design with SiGe BiCMOS Technology

The objective of this research is to study and leverage the unique properties and advantages of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) integrated circuit technologies to better design radio frequency (RF) and millimeter wave (mm-wave) circuit components. With recent developments, the high yield and modest cost silicon-based semiconductor technologies have proven to be attractive and cost-effective alternatives to high-performance III-V technology platforms. Between SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology and advanced RF complementary metal-oxide-semiconductor (CMOS) technology, the fundamental device-level differences between SiGe HBTs and field-effect transistors (FETs) grant SiGe HBTs clear advantages as well as unique design concerns. The work presented in this dissertation identifies several advantages and challenges on design using SiGe HBTs and provides design examples that exploit and address these unique benefits and problems with circuit component designs using SiGe HBTs.Ph.D