Virtual storage implementation on a microcomputer

Virtual storage is a hardware memory management technique which is gaining popularity amongst modern mainframe computers and top of the range minicomputers. It offers huge memory resources at lower cost in comparison to solid state memories of compatible size. The associated benefits are reduced component counts and lower power requirement. The trade off for the above mentioned advantages is an increase in the memory average access time. However this increase in the average access time does not appear to be a major handicap for many computer applications. With the widespread acceptance of microcomputer systems these days, more sophisticated and increasingly more complex programmes are being run on microcomputers. Demands are placed on the microcomputers for bigger memory recourses. Also the new generation microprocessors can now cater for an addressing space of many mega bytes. It is obvious that virtual storage technique is ideally suited for these new generation microprocessors since a large real memory implementation is impracticable and is out of question economically. This project investigated the feasibility of adapting an existing IMP-16C microcomputer system into a virtual storage system, assuming that a microcomputer system is single user orientated. Some of the virtual storage techniques were reviewed, in particular those that have been studied with a computer simulation of a virtual storage system. A working virtual storage computer system was implemented on the National Semiconductor IMP-16C microcomputer. the results of the simulation study. The design was based on A virtual memory of 256 K words of 16 bits was achieved. The cost to equip a system with an equivalent size real memory is about ten times the cost to manufacture the virtual storage controller. The average access time of the virtual storage computer system as implemented is an order higher than the conventional real memory system. Supplementary techniques and faster auxiliary storage can be employed to improve the average access time. This project demonstrated that a virtual storage controller can be coupled to an existing microprocessor to provide virtual memory storage at about one tenth the cost to provide the equivalent real memory storage. The virtual storage controller can be divided quite readily into functional blocks. Each block is suitable for chip level integration with LSI or VLSI technology. Implementing a virtual storage system around an existing microprocessor would be a much simpler task when these functional chips are available.Thesis (MESc) -- University of Adelaide, Department of Electrical Engineering, 198

Multicomputer communication system

A local area network is provided for a plurality of autonomous computers which operate at different rates and under different protocols coupled by network bus adapters to a global bus. A host computer (HC) divides a message file to be transmitted into blocks, each with a header that includes a data type identifier and a trailer. The associated network bus adapter (NBA) then divides the data into packets, each with a header to which a transport header and trailer is added with frame type code which specifies one of three modes of addressing in the transmission of data, namely a physical address mode for computer to computer transmission using two bytes for source and destination addresses, a logical address mode and a data type mode. In the logical address mode, one of the two addressing bytes contains a logical channel number (LCN) established between the transmitting and one or more receiving computers. In the data type mode, one of the addressing bytes contains a code identifying the type of data

Adaptive Latency Insensitive Protocols

Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

Cross-layer system reliability assessment framework for hardware faults

System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.Peer ReviewedPostprint (author's final draft

Software-Based Self-Test of Set-Associative Cache Memories

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set-associative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: 1) test patterns which must be composed of valid instruction opcodes and 2) test result observability: the results can only be observed through the results of executed instructions. For these reasons, the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologie