Iridium ADC

Today\u27s modern digital audio systems are pushing performance boundaries. Most high quality audio digital to analog converters are capable of 24 bit, 96 kHz conversion. Professional audio interfaces frequently use 24 or 32 bit 192 kHz sample rates. These systems are able to achieve dynamic ranges greater than 100 dB, and distortion on the magnitude of single parts per million. This project proposes a high resolution analog digital converter (ADC) to measure and characterize these types of devices. The proposed system will be capable of 24 bit conversion and an extended frequency range compared to the typical 20 Hz to 20 kHz audio band. This allows for a theoretical dynamic range of over 140 dB, ensuring the systems noise performance is limited by other factors. The extended frequency response offers several benefits: 1. Measurement of distortion products that occur on fundamental frequencies above 10kHz. Even though these products are not necessarily audible, they should be observed if present. 2. Observation of out-of-band oscillations, interference, or other noise. Various issues in a device could result in unintentional self oscillation which will likely be at a greater frequency than conventional audio measurement equipment operating at a maximum of 192kHz can observe. 3. Measurement of non-audio signals. Many common signals operate in the tens or hundreds of kHz range. Switch mode power supplies operate in frequencies of 100kHz and up [1]. Industrial, scientific, and medical equipment may use ultrasonic equipment, and vibration or resonant analysis may produce signals that go well beyond 20 kHz [2]. The digitized data will be transferred over USB, and a custom program will display the data in time and frequency domain simultaneously. This interface also enables control over the sampling and data processing parameters

Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

Doctor of Philosophy

dissertationAdvancements in process technology and circuit techniques have enabled the creation of small chemical microsystems for use in a wide variety of biomedical and sensing applications. For applications requiring a small microsystem, many components can be integrated onto a single chip. This dissertation presents many low-power circuits, digital and analog, integrated onto a single chip called the Utah Microcontroller. To guide the design decisions for each of these components, two specific microsystems have been selected as target applications: a Smart Intravaginal Ring (S-IVR) and an NO releasing catheter. Both of these applications share the challenging requirements of integrating a large variety of low-power mixed-signal circuitry onto a single chip. These applications represent the requirements of a broad variety of small low-power sensing systems. In the course of the development of the Utah Microcontroller, several unique and significant contributions were made. A central component of the Utah Microcontroller is the WIMS Microprocessor, which incorporates a low-power feature called a scratchpad memory. For the first time, an analysis of scaling trends projected that scratchpad memories will continue to save power for the foreseeable future. This conclusion was bolstered by measured data from a fabricated microcontroller. In a 32 nm version of the WIMS Microprocessor, the scratchpad memory is projected to save ~10-30% of memory access energy depending upon the characteristics of the embedded program. Close examination of application requirements informed the design of an analog-to-digital converter, and a unique single-opamp buffered charge scaling DAC was developed to minimize power consumption. The opamp was designed to simultaneously meet the varied demands of many chip components to maximize circuit reuse. Each of these components are functional, have been integrated, fabricated, and tested. This dissertation successfully demonstrates that the needs of emerging small low-power microsystems can be met in advanced process nodes with the incorporation of low-power circuit techniques and design choices driven by application requirements

Ultra-low power incremental delta-sigma analog-to-digital converter for self-powered sensor applications

Tässä työssä esitetään ultramatalatehoinen inkrementaalinen delta-sigma-analogia-digitaalimuunnin. Muunnin on suunniteltu 0,18 μm:n CMOS-teknologialla, ja se toimii 1,2 V :n käyttöjännitteellä ja 5 kHz:n kellotaajuudella. Differentiaalinen tulosignaali on käytännössä dc:llä, ja se vaihtelee 600 mV :n yhteismuotoisen jännitteen ympärillä -850 mV :sta 850 mV :iin. Delta-sigmamodulaattorissa käytetään kaksiasteista takaisinkytkettyä integraattorikaskadirakennetta, joka on toteutettu kytketty-kondensaattori-integraattoreilla ja yksibittisellä kvantisoijalla. Muuntimen kvantisointikohinavaatimuksien täyttyminen varmistettiin valitsemalla sopivat kertoimet ja ylinäytteistyssuhde käyttäen MATLAB-simulaatioita yhdessä modulaattorin ideaalisen mallin kanssa. Vahvistinten vähimmäisvaatimukset määritettiin makromallitason simuloinneilla ja kytkinten epäideaalisuudet analysoitiin transistoritason simuloinneilla. Varausinjektion huomattiin aiheuttavan piirissä merkittävää harmonista säröä, joten alalevyn näytteistystä (bottom plate sampling) käytettiin signaaliriippuvan varausinjektion välttämiseksi. Lisäksi ensimmäisen integraattorin vahvistimen tulonsiirrosjännitteen ja matalataajuisen kohinan vähentämiseksi käytettiin hakkuristabilointia (chopper stabilization). Muuntimen suorituskykyä analysoitiin eri prosessikulmissa lämpötiloissa −40 ◦ C, 27 ◦ C ja 85 ◦ C, ja epäsovitusherkkyys määritettiin Monte Carlo -analyysin avulla. Simulaatiotulokset sekä piirikuvion perusteella lasketut parasiittiset resistanssit ja kapasitanssit huomioonottaen, että ilman, osoittavat piirin olevan stabiili ja täyttävän tarkkuusvaatimukset kaikissa simuloiduissa kulmissa. Monta Carlo -analyysin perusteella signaali-kohinasuhde on vähintään 80,05 dB:ä ja harmonisen särön kokonaismäärä on enintään -80.89 dB:ä. Tehonkulutus ei ylitä 1,2 μA:a missään simulaatiossa.In this thesis an ultra-low power incremental delta-sigma analog-to-digital converter is presented. The converter is designed in 0.18 μm CMOS technology with a single 1.2 V supply voltage, and it operates with a 5 kHz clock signal. The differential input signal to the converter is virtually dc, and it varies from −850 mV to 850 mV around a common-mode voltage of 600 mV . The delta-sigma modulator has a second order cascade-of-integrators feedback structure, which is realized with switched-capacitor integrators and a one-bit quantizer. The converter’s quantization noise requirement is met by appropriate choice of coefficients and oversampling ratio, based on MATLAB simulations on an ideal model of the modulator. The minimum requirements of the amplifiers were determined from simulations with macromodels, and the switch non-idealities were analyzed in transistor-level simulations. It was noticed that switch charge injection causes significant harmonic distortion in the circuit, hence bottom plate sampling was implemented to eliminate the signal-dependent charge injection. Furthermore, the offset and low-frequency noise in the first integrator were attenuated by means of chopper stabilization. The converter’s performance is analyzed in different process corners, at −40◦ C, 27◦ C, and 85◦ C, and its process mismatch sensitivity is determined via Monte Carlo analysis. The results obtained from both pre- and post-layout simulations indicate complete stability, and acceptable accuracy in all design corners. The minimum signal-to-noise and distortion ratio obtained from corner analysis, is 80.05 dB, which is enhanced up to 7 dB in the best corner, and maximum harmonic distortion is below −80.89 dB. Moreover, the power consumption of the converter did not exceed 1.2 μW in any of the simulations

Error modeling, self-calibration and design of pipelined analog to digital converters

Typescript (photocopy).As the field of signal processing accelerates toward the use of high performance digital techniques, there is a growing need for increasingly fast and accurate analog to digital converters. Three highly visible examples of this trend originated in the last decade. The advent of the compact disc revolutionized the way high-fidelity audio is stored, reproduced, recorded and processed. Digital communication links, fiber optic cables and in the near future ISDN networks (Integrated Services Digital Network) are steadily replacing major portions of telephone systems. Finally, video-conferencing, multi-media computing and currently emerging high definition television (HDTV) systems rely more and more on real-time digital data compression and image enhancing techniques. All these applications rely on analog to digital conversion. In the field of digital audio, the required conversion accuracy is high, but the conversion speed limited (16 bits, 2 x 20 kHz signal bandwidth). In the field of image processing, the required accuracy is less, but the data conversion speed high (8-10 bits, 5-20MHz bandwidth). New applications keep pushing for increasing conversion rates and simultaneously higher accuracies. This dissertation discusses new analog to digital converter architectures that could accomplish this. As a consequence of the trend towards digital processing, prominent analog designers throughout the world have engaged in very active research on the topic of data conversion. Unfortunately, literature has not always kept up. At the time of this writing, it seemed rather difficult to find detailed fundamental publications about analog to digital converter design. This dissertation represents a modest attempt to remedy this situation. It is hoped that anyone with a back-ground in analog design could go through this work and pick up the fundamentals of converter operation, as well as a number of more advanced design techniques

Radiation-Hardened Data Acquisition System Based on a Mask-programmable Analog Array

Data acquisition systems capable of extreme temperature and radiation environments are of dire need in an era of great nuclear energy generation. Efforts to respond to recent nuclear accidents, such as those caused by natural disasters at Fukushima, have suffered in promptness and effectiveness due to the lack of information gathered from these sites. Currently, there are no systems available that accurately acquire, digitize, and remotely report this data in the presence of harsh radiation. Using a mask-programmable analog array prototype chip designed for Triad Semiconductor and an FMI frequency synthesizer, both verified to beyond 300 kRad and 125ºC and capable of analog signal conditioning and digitization, a radiation-hardened data acquisition system is produced. This system will report three parameters of importance to the assessment of a nuclear reactor environment: gamma radiation, temperature, and pressure. Through a three-task development process, the discrete part selection and overall system will be outlined, detailed board design will be shown, and end-to-end system calibration and radiation testing will be performed and analyzed. The evaluation of target environments will provide specifications for system performance, as well as determine successful completion of the work

Low-Power Low-Noise CMOS Analog and Mixed-Signal Design towards Epileptic Seizure Detection

About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

Integrated temperature sensors in deep sub-micron CMOS technologies

textIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Electrical and Computer Engineerin