A TMS320C54 system for effective online Signature Verification using Hidden Markov Models

In this paper we present a scheme for real time implementation of a Hidden Markov Model based Signature Verification System on a TMS320C54 processor. Here we explain in detail our overall methodology and the subsequent DSP implementation. We also propose two new algorithms which would further facilitate real-time operation. We use the Baum-We1ch Algorithm for training the HMM and the Viterbi Algorithm for the testing of our proposed system. It may be noted that the technique of HMMs have hitherto been applied for speech modelling and only recently has its application to the field of Signature Verification been considered. Our proposed system has an overall accuracy of 11.64% FAR and 0.64% FRR

Validation & Verification of an EDA automated synthesis tool

Reliability and correctness are two mandatory features for automated synthesis tools. To reach the goals several campaigns of Validation and Verification (V&V) are needed. The paper presents the extensive efforts set up to prove the correctness of a newly developed EDA automated synthesis tool. The target tool, MarciaTesta, is a multi-platform automatic generator of test programs for microprocessors' caches. Getting in input the selected March Test and some architectural details about the target cache memory, the tool automatically generates the assembly level program to be run as Software Based Self-Testing (SBST). The equivalence between the original March Test, the automatically generated Assembly program, and the intermediate C/C++ program have been proved resorting to sophisticated logging mechanisms. A set of proved libraries has been generated and extensively used during the tool development. A detailed analysis of the lessons learned is reporte

Hardware/software codesign methodology for fuzzy controller implementation

This paper describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed by a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC