Measurements, Models, Systems and Design

531 s.

Real-Time Machine Learning Based Open Switch Fault Detection and Isolation for Multilevel Multiphase Drives

Due to the rapid proliferation interest of the multiphase machines and their combination with multilevel inverters technology, the demand for high reliability and resilient in the multiphase multilevel drives is increased. High reliability can be achieved by deploying systematic preventive real-time monitoring, robust control, and efficient fault diagnosis strategies. Fault diagnosis, as an indispensable methodology to preserve the seamless post-fault operation, is carried out in consecutive steps; monitoring the observable signals to generate the residuals, evaluating the observations to make a binary decision if any abnormality has occurred, and identifying the characteristics of the abnormalities to locate and isolate the failed components. It is followed by applying an appropriate reconfiguration strategy to ensure that the system can tolerate the failure. The primary focus of presented dissertation was to address employing computational and machine learning techniques to construct a proficient fault diagnosis scheme in multilevel multiphase drives. First, the data-driven nonlinear model identification/prediction methods are used to form a hybrid fault detection framework, which combines module-level and system-level methods in power converters, to enhance the performance and obtain a rapid real-time detection. Applying suggested nonlinear model predictors along with different systems (conventional two-level inverter and three-level neutral point clamped inverter) result in reducing the detection time to 1% of stator current fundamental period without deploying component-level monitoring equipment. Further, two methods using semi-supervised learning and analytical data mining concepts are presented to isolate the failed component. The semi-supervised fuzzy algorithm is engaged in building the clustering model because the deficient labeled datasets (prior knowledge of the system) leads to degraded performance in supervised clustering. Also, an analytical data mining procedure is presented based on data interpretability that yields two criteria to isolate the failure. A key part of this work also dealt with the discrimination between the post-fault characteristics, which are supposed to carry the data reflecting the fault influence, and the output responses, which are compensated by controllers under closed-loop control strategy. The performance of all designed schemes is evaluated through experiments

Automating the IEEE std. 1500 compliance verification for embedded cores

The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standar

Power supply ramping for quasi-static testing of PLLs

An innovative approach for testing PLLs in open loop-mode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are forced into various regions of operation causing the sensitivity of the faults to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing

Analog sinewave signal generators for mixed-signal built-in test applications

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.Gobierno de España TEC2007-68072/MIC, TSI-020400-2008-71/MEDEA+2A105, CATRENE CT302Junta de Andalucía P09-TIC-538

Modelling of Pencil-Lead Break Acoustic Emission Sources using the Time Reversal Technique

In Acoustic Emissions (AE), Hsu-Nielsen Pencil-Lead Breaks (PLB) are used to generate sound waves enabling the characterization of acoustic wave speed in complex structures. The broadband signal of a PLB represents a repeatable emission, which can be applied at different regions of the structure, and therefore can be used to calibrate the localization algorithms of the AE system. In recent years, the use of Finite Element Method (FEM) has flourished for modelling acoustic Lamb wave propagation, which is present in thin plate-like structures. The primary challenge faced by the AE community is the lack of a well-known mathematical function of a PLB signal that can be applied in numerical simulations. This study makes use of a Time Reversal (TR) approach to identify the emission source of the PLB on a 7075-T651 aluminum plate. An ABAQUS CAETM model with piezoelectric actuators and sensors was developed. In order to avoid edge reflections, absorbing boundaries based on the Stiffness Reduction Method (SRM) were considered. The captured PLB signals were used as input to the FEM and was time-reversed. Furthermore, a band-limited white noise signal was used to calibrate the contribution of the broadband frequencies found in the transmitted wave packet. Preliminary results indicate that the TR approach can be used to understand the shape and function of the original transmitted signal

A clinical patient vital signs parameter measurement, processing and predictive algorithm using ECG

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In the modern clinical and healthcare setting, the electronic collection and analysis of patient related vital signs and parameters are a fundamental part of the relevant treatment plan and positive patient response. Modern analytical techniques combined with readily available computer software today allow for the near real time analysis of digitally acquired measurements. In the clinical context, this can directly relate to patient survival rates and treatment success. The processing of clinical parameters, especially the Electrocardiogram (ECG) in the critical care setting has changed little in recent years and the analytical processes have mostly been managed by highly trained and experienced cardiac specialists. Warning, detection and measurement techniques are focused on the post processing of events relying heavily on averaging and analogue filtering to accurately capture waveform morphologies and deviations. This Ph.D. research investigates an alternative and the possibility to analyse, in the digital domain, bio signals with a focus on the ECG to determine if the feasibility of bit by bit or near real time analysis is indeed possible but more so if the data captured has any significance in the analysis and presentation of the wave patterns in a patient monitoring environment. The research and experiments have shown the potential for the development of logical models that address both the detection and short term predication of possible follow-on events with a focus on Myocardial Ischemic (MI) and Infraction based deviations. The research has shown that real time waveform processing compared to traditional graph based analysis, is both accurate and has the potential to be of benefit to the clinician by detecting deviations and morphologies in a real time domain. This is a significant step forward and has the potential to embed years of clinical experience into the measurement processes of clinical devices, in real terms. Also, providing expert analytical and identification input electronically at the patient bedside. The global human population is testing the healthcare systems and care capabilities with the shortage of clinical and healthcare providers in ever decreasing coverage of treatment that can be provided. The research is a moderate step in further realizing this and aiding the caregiver by providing true and relevant information and data, which assists in the clinical decision process and ultimately improving the required standard of patient care

Moving Towards Analog Functional Safety

Over the past century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power systems. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The standard ISO 26262 related to functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardizing fault modeling, injection and simulation mainly focused on digital circuits and disregarding analog ones. An initial attempt is being made with the IEEE P2427 standard draft standard that started to give this field a structured and formal organization. In this context, new fault models, injection, and abstraction methodologies for analog circuits are proposed in this thesis to enhance this application field. The faults proposed by the IEEE P2427 standard draft standard are initially evaluated to understand the associated fault behaviors during the simulation. Moreover, a novel approach is presented for modeling realistic stuck-on/off defects based on oxide defects. These new defects proposed are required because digital stuck-at-fault models where a transistor is frozen in on-state or offstate may not apply well on analog circuits because even a slight variation could create deviations of several magnitudes. Then, for validating the proposed defects models, a novel predictive fault grouping based on faulty AC matrices is applied to group faults with equivalent behaviors. The proposed fault grouping method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself to faulty AC simulations. Using AC simulations results in two different methods that allow grouping faults with the same frequency response are presented. The first method is an AC-based grouping method that exploits the potentialities of the S-parameters ports. While the second is a Circle-based grouping based on the circle-fitting method applied to the extracted AC matrices. Finally, an open-source framework is presented for the fault injection and manipulation perspective. This framework relies on the shared semantics for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. As a use case for the proposed framework, a process of analog fault injection is discussed. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. The framework is entirely written in C++, and its APIs are also interfaced with Python. The entire framework is open-source and available on GitHub. The last part of the thesis presents abstraction methodologies that can abstract transistor level models into Verilog-AMS models and Verilog- AMS piecewise and nonlinear models into C++. These abstracted models can be integrated into heterogeneous systems. The purpose of integration is the simulation of heterogeneous components embedded in a Virtual Platforms (VP) needs to be fast and accurate

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures