Implementation of the Trigonometric LMS Algorithm using Original Cordic Rotation

The LMS algorithm is one of the most successful adaptive filtering algorithms. It uses the instantaneous value of the square of the error signal as an estimate of the mean-square error (MSE). The LMS algorithm changes (adapts) the filter tap weights so that the error signal is minimized in the mean square sense. In Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS), two new versions of LMS algorithms, same formulations are performed as in the LMS algorithm with the exception that filter tap weights are now expressed using trigonometric and hyperbolic formulations, in cases for TLMS and HLMS respectively. Hence appears the CORDIC algorithm as it can efficiently perform trigonometric, hyperbolic, linear and logarithmic functions. While hardware-efficient algorithms often exist, the dominance of the software systems has kept those algorithms out of the spotlight. Among these hardware- efficient algorithms, CORDIC is an iterative solution for trigonometric and other transcendental functions. Former researches worked on CORDIC algorithm to observe the convergence behavior of Trigonometric LMS (TLMS) algorithm and obtained a satisfactory result in the context of convergence performance of TLMS algorithm. But revious researches directly used the CORDIC block output in their simulation ignoring the internal step-by-step rotations of the CORDIC processor. This gives rise to a need for verification of the convergence performance of the TLMS algorithm to investigate if it actually performs satisfactorily if implemented with step-by-step CORDIC rotation. This research work has done this job. It focuses on the internal operations of the CORDIC hardware, implements the Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS) algorithms using actual CORDIC rotations. The obtained simulation results are highly satisfactory and also it shows that convergence behavior of HLMS is much better than TLMS.Comment: 12 pages, 5 figures, 1 table. Published in IJCNC; http://airccse.org/journal/cnc/0710ijcnc08.pdf, http://airccse.org/journal/ijc2010.htm

Efficient Adaptive Filter Algorithms Using Variable Tap-length Scheme

Today the usage of digital signal processors has increased, where adaptive filter algorithms are now routinely employed in mostly all contemporary devices such as mobile phones, camcorders, digital cameras, and medical monitoring equipment, to name few. The filter tap-length, or the number of taps, is a significant structural parameter of adaptive filters that can influences both the complexity and steady-state performance characteristics of the filter. Traditional implementation of adaptive filtering algorithms presume some fixed filter-length and focus on estimating variable filter\u27s tap-weights parameters according to some pre-determined cost function. Although this approach can be adequate in some applications, it is not the case in more complicated ones as it does not answer the question of filter size (tap-length). This problem can be more apparent when the application involves a change in impulse response, making it hard for the adaptive filter algorithm to achieve best potential performance. A cost-effective approach is to come up with variable tap-length filtering scheme that can search for the optimal length while the filter is adapting its coefficients. In direct form structure filtering, commonly known as a transversal adaptive filter, several schemes were used to estimate the optimum tap-length. Among existing algorithms, pseudo fractional tap-length (FT) algorithm, is of particular interest because of its fast convergence rate and small steady-state error. Lattice structured adaptive filters, on the other hand, have attracted attention recently due to a number of desirable properties. The aim of this research is to develop efficient adaptive filter algorithms that fill the gap where optimal filter structures were not proposed by incorporating the concept of pseudo fractional tap-length (FT) in adaptive filtering algorithms. The contribution of this research include the development of variable length adaptive filter scheme and hence optimal filter structure for the following applications: (1) lattice prediction; (2) Least-Mean-Squares (LMS) lattice system identification; (3) Recursive Least-Squares (RLS) lattice system identification; (4) Constant Modulus Algorithm (CMA) blind equalization. To demonstrate the capability of proposed algorithms, simulations examples are implemented in different experimental conditions, where the results showed noticeable improvement in the context of mean square Error (MSE), as well as in the context of convergence rate of the proposed algorithms with their counterparts adaptive filter algorithms. Simulation results have also proven that with affordable extra computational complexity, an optimization for both of the adaptive filter coefficients and the filter tap-length can be attained

Adaptive Interference Mitigation in GPS Receivers

Satellite navigation systems (GNSS) are among the most complex radio-navigation systems, providing positioning, navigation, and timing (PNT) information. A growing number of public sector and commercial applications rely on the GNSS PNT service to support business growth, technical development, and the day-to-day operation of technology and socioeconomic systems. As GNSS signals have inherent limitations, they are highly vulnerable to intentional and unintentional interference. GNSS signals have spectral power densities far below ambient thermal noise. Consequently, GNSS receivers must meet high standards of reliability and integrity to be used within a broad spectrum of applications. GNSS receivers must employ effective interference mitigation techniques to ensure robust, accurate, and reliable PNT service. This research aims to evaluate the effectiveness of the Adaptive Notch Filter (ANF), a precorrelation mitigation technique that can be used to excise Continuous Wave Interference (CWI), hop-frequency and chirp-type interferences from GPS L1 signals. To mitigate unwanted interference, state-of-the-art ANFs typically adjust a single parameter, the notch centre frequency, and zeros are constrained extremely close to unity. Because of this, the notch centre frequency converges slowly to the target frequency. During this slow converge period, interference leaks into the acquisition block, thus sabotaging the operation of the acquisition block. Furthermore, if the CWI continuously hops within the GPS L1 in-band region, the subsequent interference frequency is locked onto after a delay, which means constant interference occurs in the receiver throughout the delay period. This research contributes to the field of interference mitigation at GNSS's receiver end using adaptive signal processing, predominately for GPS. This research can be divided into three stages. I first designed, modelled and developed a Simulink-based GPS L1 signal simulator, providing a homogenous test signal for existing and proposed interference mitigation algorithms. Simulink-based GPS L1 signal simulator provided great flexibility to change various parameters to generate GPS L1 signal under different conditions, e.g. Doppler Shift, code phase delay and amount of propagation degradation. Furthermore, I modelled three acquisition schemes for GPS signals and tested GPS L1 signals acquisition via coherent and non-coherent integration methods. As a next step, I modelled different types of interference signals precisely and implemented and evaluated existing adaptive notch filters in MATLAB in terms of Carrier to Noise Density (\u1d436/\u1d4410), Signal to Noise Ratio (SNR), Peak Degradation Metric, and Mean Square Error (MSE) at the output of the acquisition module in order to create benchmarks. Finally, I designed, developed and implemented a novel algorithm that simultaneously adapts both coefficients in lattice-based ANF. Mathematically, I derived the full-gradient term for the notch's bandwidth parameter adaptation and developed a framework for simultaneously adapting both coefficients of a lattice-based adaptive notch filter. I evaluated the performance of existing and proposed interference mitigation techniques under different types of interference signals. Moreover, I critically analysed different internal signals within the ANF structure in order to develop a new threshold parameter that resets the notch bandwidth at the start of each subsequent interference frequency. As a result, I further reduce the complexity of the structural implementation of lattice-based ANF, allowing for efficient hardware realisation and lower computational costs. It is concluded from extensive simulation results that the proposed fully adaptive lattice-based provides better interference mitigation performance and superior convergence properties to target frequency compared to traditional ANF algorithms. It is demonstrated that by employing the proposed algorithm, a receiver is able to operate with a higher dynamic range of JNR than is possible with existing methods. This research also presents the design and MATLAB implementation of a parameterisable Complex Adaptive Notch Filer (CANF). Present analysis on higher order CANF for detecting and mitigating various types of interference for complex baseband GPS L1 signals. In the end, further research was conducted to suppress interference in the GPS L1 signal by exploiting autocorrelation properties and discarding some portion of the main lobe of the GPS L1 signal. It is shown that by removing 30% spectrum of the main lobe, either from left, right, or centre, the GPS L1 signal is still acquirable

Real-time neural signal processing and low-power hardware co-design for wireless implantable brain machine interfaces

Intracortical Brain-Machine Interfaces (iBMIs) have advanced significantly over the past two decades, demonstrating their utility in various aspects, including neuroprosthetic control and communication. To increase the information transfer rate and improve the devices’ robustness and longevity, iBMI technology aims to increase channel counts to access more neural data while reducing invasiveness through miniaturisation and avoiding percutaneous connectors (wired implants). However, as the number of channels increases, the raw data bandwidth required for wireless transmission also increases becoming prohibitive, requiring efficient on-implant processing to reduce the amount of data through data compression or feature extraction. The fundamental aim of this research is to develop methods for high-performance neural spike processing co-designed within low-power hardware that is scaleable for real-time wireless BMI applications. The specific original contributions include the following: Firstly, a new method has been developed for hardware-efficient spike detection, which achieves state-of-the-art spike detection performance and significantly reduces the hardware complexity. Secondly, a novel thresholding mechanism for spike detection has been introduced. By incorporating firing rate information as a key determinant in establishing the spike detection threshold, we have improved the adaptiveness of spike detection. This eventually allows the spike detection to overcome the signal degradation that arises due to scar tissue growth around the recording site, thereby ensuring enduringly stable spike detection results. The long-term decoding performance, as a consequence, has also been improved notably. Thirdly, the relationship between spike detection performance and neural decoding accuracy has been investigated to be nonlinear, offering new opportunities for further reducing transmission bandwidth by at least 30% with minor decoding performance degradation. In summary, this thesis presents a journey toward designing ultra-hardware-efficient spike detection algorithms and applying them to reduce the data bandwidth and improve neural decoding performance. The software-hardware co-design approach is essential for the next generation of wireless brain-machine interfaces with increased channel counts and a highly constrained hardware budget. The fundamental aim of this research is to develop methods for high-performance neural spike processing co-designed within low-power hardware that is scaleable for real-time wireless BMI applications. The specific original contributions include the following: Firstly, a new method has been developed for hardware-efficient spike detection, which achieves state-of-the-art spike detection performance and significantly reduces the hardware complexity. Secondly, a novel thresholding mechanism for spike detection has been introduced. By incorporating firing rate information as a key determinant in establishing the spike detection threshold, we have improved the adaptiveness of spike detection. This eventually allows the spike detection to overcome the signal degradation that arises due to scar tissue growth around the recording site, thereby ensuring enduringly stable spike detection results. The long-term decoding performance, as a consequence, has also been improved notably. Thirdly, the relationship between spike detection performance and neural decoding accuracy has been investigated to be nonlinear, offering new opportunities for further reducing transmission bandwidth by at least 30\% with only minor decoding performance degradation. In summary, this thesis presents a journey toward designing ultra-hardware-efficient spike detection algorithms and applying them to reduce the data bandwidth and improve neural decoding performance. The software-hardware co-design approach is essential for the next generation of wireless brain-machine interfaces with increased channel counts and a highly constrained hardware budget.Open Acces

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.The research leading to these results has received funding from the Spanish Government and European FEDER funds (DPI2012-32390), the Valencia Regional Government (PROMETEO/2013/085) and the University of Alicante (GRE12-17)

IMPLEMENTATION OF NOISE CANCELLATION WITH HARDWARE DESCRIPTION LANGUAGE

The objective of this project is to implement noise cancellation technique on an FPGA using Hardware Description Language. The performance of several adaptive algorithms is compared to determine the desirable algorithm used for adaptive noise cancellation system. The project will focus on the implementation of adaptive filter with least-meansquares (LMS) algorithm or normalized least-mean-squares (NLMS) algorithm to cancel acoustic noises. This noise consists of extraneous or unwanted waveforms that can interfere with communication. Due to the simplicity and effectiveness of adaptive noise cancellation technique, it is used to remove the noise component from the desired signal. The project is divided into four main parts: research, Matlab simulation, ModelSim simulation and hardware implementation. The project starts with research on several noise cancellation techniques, and then with Matlab code, Simulink and FDA tool, the adaptive noise cancellation system is designed with the implementation of the LMS algorithm, NLMS algorithm and recursive-least-square algorithm to remove the interference noise. By using the Matlab code and Simulink, the noise that interfered with a sinusoidal signal and a record of music can be removed. The original signal in turns can be retrieved from the noise corrupted signal by changing the coefficient of the filter. Since filter is the important component in adaptive filtering process, the filter is designed first before adding adaptive algorithm. A Finite Impulse Response (FIR) filter is designed and the desired result of functional simulation and timing simulation is obtained through ModelSim and Integrated Software Environment (ISE) software and FPGA implementation. Finally the adaptive algorithm is added to the filter, and implemented in the FPGA. The noise is greatly reduced in Matlab simulation, functional simulation and timing simulation. Hence the results of this project show that noise cancellation with adaptive filter is feasible

Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications

Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge in real-time image processing systems, requiring high computing capacity, usually not available in processors for embedded systems. Hardware acceleration is therefore crucial, and devices such as Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. These devices can assist embedded processors by significantly speeding-up computationally intensive software algorithms. Moreover, critical applications introduce strict requirements not only from the real-time constraints, but also from the device reliability and algorithm robustness points of view. Technology scaling is highlighting reliability problems related to aging phenomena, and to the increasing sensitivity of digital devices to external radiation events that can cause transient or even permanent faults. These faults can lead to wrong information processed or, in the worst case, to a dangerous system failure. In this context, the reconfigurable nature of FPGA devices can be exploited to increase the system reliability and robustness by leveraging Dynamic Partial Reconfiguration features. The research work presented in this thesis focuses on the development of techniques for implementing efficient and robust real-time embedded image processing hardware accelerators and systems for mission-critical applications. Three main challenges have been faced and will be discussed, along with proposed solutions, throughout the thesis: (i) achieving real-time performances, (ii) enhancing algorithm robustness, and (iii) increasing overall system's dependability. In order to ensure real-time performances, efficient FPGA-based hardware accelerators implementing selected image processing algorithms have been developed. Functionalities offered by the target technology, and algorithm's characteristics have been constantly taken into account while designing such accelerators, in order to efficiently tailor algorithm's operations to available hardware resources. On the other hand, the key idea for increasing image processing algorithms' robustness is to introduce self-adaptivity features at algorithm level, in order to maintain constant, or improve, the quality of results for a wide range of input conditions, that are not always fully predictable at design-time (e.g., noise level variations). This has been accomplished by measuring at run-time some characteristics of the input images, and then tuning the algorithm parameters based on such estimations. Dynamic reconfiguration features of modern reconfigurable FPGA have been extensively exploited in order to integrate run-time adaptivity into the designed hardware accelerators. Tools and methodologies have been also developed in order to increase the overall system dependability during reconfiguration processes, thus providing safe run-time adaptation mechanisms. In addition, taking into account the target technology and the environments in which the developed hardware accelerators and systems may be employed, dependability issues have been analyzed, leading to the development of a platform for quickly assessing the reliability and characterizing the behavior of hardware accelerators implemented on reconfigurable FPGAs when they are affected by such faults

Performance analysis of multichannel lattice equalization in coherent underwater communications

This work examines the numerical fixed-point performance of a new multichannel lattice RLS filtering algorithm using data from two underwater acoustic communication experiments. The algorithm may be an appealing choice for underwater equalization due to its robust numerical behavior and linear scaling of the computational complexity with filter order. Simple modifications to widely-used methods for carrier/timing synchronization and symbol slicing in transversal equalizers are proposed. Experimental results show that the algorithm is as accurate as the similarly array-based QR-RLS, tolerating word lengths as low as 16-20 bits with minor degradation relative to floating-point benchmarks. These features, coupled with a very modular and regular structure, are highly desirable in energyefficient hardware or embedded implementations.FC

An efficient implementation of lattice-ladder multilayer perceptrons in field programmable gate arrays

The implementation efficiency of electronic systems is a combination of conflicting requirements, as increasing volumes of computations, accelerating the exchange of data, at the same time increasing energy consumption forcing the researchers not only to optimize the algorithm, but also to quickly implement in a specialized hardware. Therefore in this work, the problem of efficient and straightforward implementation of operating in a real-time electronic intelligent systems on field-programmable gate array (FPGA) is tackled. The object of research is specialized FPGA intellectual property (IP) cores that operate in a real-time. In the thesis the following main aspects of the research object are investigated: implementation criteria and techniques. The aim of the thesis is to optimize the FPGA implementation process of selected class dynamic artificial neural networks. In order to solve stated problem and reach the goal following main tasks of the thesis are formulated: rationalize the selection of a class of Lattice-Ladder Multi-Layer Perceptron (LLMLP) and its electronic intelligent system test-bed – a speaker dependent Lithuanian speech recognizer, to be created and investigated; develop dedicated technique for implementation of LLMLP class on FPGA that is based on specialized efficiency criteria for a circuitry synthesis; develop and experimentally affirm the efficiency of optimized FPGA IP cores used in Lithuanian speech recognizer. The dissertation contains: introduction, four chapters and general conclusions. The first chapter reveals the fundamental knowledge on computer-aideddesign, artificial neural networks and speech recognition implementation on FPGA. In the second chapter the efficiency criteria and technique of LLMLP IP cores implementation are proposed in order to make multi-objective optimization of throughput, LLMLP complexity and resource utilization. The data flow graphs are applied for optimization of LLMLP computations. The optimized neuron processing element is proposed. The IP cores for features extraction and comparison are developed for Lithuanian speech recognizer and analyzed in third chapter. The fourth chapter is devoted for experimental verification of developed numerous LLMLP IP cores. The experiments of isolated word recognition accuracy and speed for different speakers, signal to noise ratios, features extraction and accelerated comparison methods were performed. The main results of the thesis were published in 12 scientific publications: eight of them were printed in peer-reviewed scientific journals, four of them in a Thomson Reuters Web of Science database, four articles – in conference proceedings. The results were presented in 17 scientific conferences