23,903 research outputs found

    Systematic Approach to Arowana Gender Identification Problem Using Algorithm of Inventive Problem Solving (ARIZ)

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    This paper presents a systematic approach to arowana gender identification problem using algorithm of inventive problem solving (ARIZ). Arowana is a beautiful and expensive fish. Many farms try to improve their efficiency in breeding arowana, but the problem is that arowana is monomorphic, which makes it difficult to distinguish male from female just from their appearance. This causes difficulties in mating and selling of arowana. Many trial-and-error methods have been used with little success. The problem of arowana gender identification cannot be solved easily with the psychological methods such as brainstorming or trial and error, it needs a more logical and well-structured method of problem solving. In this paper, ARIZ is used to systematically analyze the problem and search for possibilities to identify the gender of arowana step by step, and finally, among 32 ideas generated, some potential solutions have been evaluated and compared with the commonly used methods with satisfactory results which demonstrate the effectiveness of ARIZ as a powerful innovative problem solving tool

    Dynamically typed languages

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    Dynamically typed languages such as Python and Ruby have experienced a rapid grown in popularity in recent times. However, there is much confusion as to what makes these languages interesting relative to statically typed languages, and little knowledge of their rich history. In this chapter I explore the general topic of dynamically typed languages, how they differ from statically typed languages, their history, and their defining features

    Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

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    The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

    NASA SBIR abstracts of 1990 phase 1 projects

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    The research objectives of the 280 projects placed under contract in the National Aeronautics and Space Administration (NASA) 1990 Small Business Innovation Research (SBIR) Phase 1 program are described. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses in response to NASA's 1990 SBIR Phase 1 Program Solicitation. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 280, in order of its appearance in the body of the report. The document also includes Appendixes to provide additional information about the SBIR program and permit cross-reference in the 1990 Phase 1 projects by company name, location by state, principal investigator, NASA field center responsible for management of each project, and NASA contract number

    TensorFlow Estimators: Managing Simplicity vs. Flexibility in High-Level Machine Learning Frameworks

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    We present a framework for specifying, training, evaluating, and deploying machine learning models. Our focus is on simplifying cutting edge machine learning for practitioners in order to bring such technologies into production. Recognizing the fast evolution of the field of deep learning, we make no attempt to capture the design space of all possible model architectures in a domain- specific language (DSL) or similar configuration language. We allow users to write code to define their models, but provide abstractions that guide develop- ers to write models in ways conducive to productionization. We also provide a unifying Estimator interface, making it possible to write downstream infrastructure (e.g. distributed training, hyperparameter tuning) independent of the model implementation. We balance the competing demands for flexibility and simplicity by offering APIs at different levels of abstraction, making common model architectures available out of the box, while providing a library of utilities designed to speed up experimentation with model architectures. To make out of the box models flexible and usable across a wide range of problems, these canned Estimators are parameterized not only over traditional hyperparameters, but also using feature columns, a declarative specification describing how to interpret input data. We discuss our experience in using this framework in re- search and production environments, and show the impact on code health, maintainability, and development speed.Comment: 8 pages, Appeared at KDD 2017, August 13--17, 2017, Halifax, NS, Canad

    Capsules and Semantic Regions for Code Visualization and Direct Manipulation of Live Programs

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    JPie is a visual programming environment supporting live construction of Java applications. Class modifications, such as declaring instance variables and overriding methods, take effect immediately on existing instances of the class to encourage experimentation in an educational setting. Because programs are edited live, editing gestures must transform the program from one well-formed state to another, without intermediate ambiguous states. To accomplish this, JPie’s visual representation provides capsules, which represent logical code units, and semantic regions, which represent different aspects of a program. A capsule’s meaning depends upon its containing semantic region. Similarly, a gesture, which involves manipulation of a capsule, is interpreted on the basis of the semantic region in which it occurs. This paper describes how capsules and semantic regions visually expose the structure of JPie programs and support live program editing through natural atomic gestures

    The delayed transformation: restructuring in the automobile, chemical, clothing and machine tool industries.

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    In this paper, we focus on the results of the Belgian Trend Study. The intention of this study was to examine the prevalence of new production concepts within the widest possible range of companies in the automobile, the machine-tool, the chemical and the clothing industries. The Trend Study aimed to answer the following questions : is the Taylorist division of labour a thing of the past ? What are the alternatives ? Are shifts in the division of labour accompanied by another type of personnel policy, and do traditional relations have to make way for this new approach ? The methodological concept used had to guarantee that the findings at the level of each industry could be generalized. Though the picture emerging from the empirical data collected in the four industrial sectors is inevitably diverse, the data make it possible merely to suggest a 'neo' rather than a 'post' Taylorist or Fordist concept.
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