Power efficient dataflow design for a heterogeneous smart camera architecture

Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low

Lazy transition systems: application to timing optimization of asynchronous circuits

The paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents necessary conditions to synthesize circuits with a correct behavior under the given timing assumptions. Preliminary results show that significant area and performance improvements can be obtained by exploiting the extra "don't care" space implicitly provided by the laziness of the events.Peer ReviewedPostprint (author's final draft

Cybersecurity and Quantum Computing: friends or foes?

L'abstract è presente nell'allegato / the abstract is in the attachmen

Criteria for the Design of "fast," "safe" Asynchronous Sequential Fluidic Circuits

Engineerin

Asynchronous Logic Design with Flip-Flop Constraints

Some techniques are presented to permit the implementation of asynchronous sequential circuits using standard flip-flops. An algorithm is presented for the RS flip-flop, and it is shown that any flow table may be realized using the algorithm (the flow table is assumed to be realizable using standard logic gates). The approach is shown to be directly applicable to synchronous circuits, and transition flip-flops (JK, D, and T) are analyzed using the ideas developed. Constraints are derived for the flow tables to meet to be realizable using transition flip-flops in asynchronous situations, and upper and lower bounds on the number of transition flip-flops required to implement a given flow table are stated

Some recent asynchronous system design methodologies

Journal ArticleWe present an in-depth study of some techniques for asynchronous system design, analysis, and verification. After defining basic terminology, we take one simple example - a four-phase t o two-phase converter - and present its design using (a) classical flow-tables; (b) Signal Transition Graphs of [8]; and (c) Trace Theory of [15]. We then present necessary and sufficient conditions for Delay Insensitivity, proposed by [38], and illustrate it on our example. Finally, we present the work of [13] on the verification of asynchronous circuits, and illustrate it on the circuits derived in the paper. The following points are emphasized: (i) presentation of techniques at more depth than in a general survey; (ii) illustration of all t h e aspects discussed on a common example; (hi) comparative study of the works presented. Many interesting works had to be left out, solely because of our lack of space and time

Development of Activity in the Mouse Visual Cortex.

A comprehensive developmental timeline of activity in the mouse cortex in vivo is lacking. Understanding the activity changes that accompany synapse and circuit formation is important to understand the mechanisms by which activity molds circuits and would help to identify critical checkpoints for normal development. To identify key principles of cortical activity maturation, we systematically tracked spontaneous and sensory-evoked activity with extracellular recordings of primary visual cortex (V1) in nonanesthetized mice. During the first postnatal week (postnatal days P4–P7), V1 was not visually responsive and exhibited long (>10 s) periods of network silence. Activation consisted exclusively of “slow-activity transients,” 2–10 s periods of 6–10 Hz “spindle-burst' oscillations; the response to spontaneous retinal waves. By tracking daily changes in this activity, two key components of spontaneous activity maturation were revealed: (1) spindle-burst frequency acceleration (eventually becoming the 20–50 Hz broadband activity caused by the asynchronous state) and (2) “filling-in” of silent periods with low-frequency (2–4 Hz) activity (beginning on P10 and complete by P13). These two changes are sufficient to create the adult-like pattern of continuous activity, alternation between fast-asynchronous and slow-synchronous activity, by eye opening. Visual responses emerged on P8 as evoked spindle-bursts and neuronal firing with a signal-to-noise ratio higher than adult. Both were eliminated by eye opening, leaving only the mature, short-latency response. These results identify the developmental origins of mature cortical activity and implicate the period before eye opening as a critical checkpoint. By providing a systematic description of electrical activity development, we establish the murine visual cortex as a model for the electroencephalographic development of fetal humans. SIGNIFICANCE STATEMENT Cortical activity is an important indicator of long-term health and survival in preterm infants and molds circuit formation, but gaps remain in our understanding of the origin and normal progression of this activity in the developing cortex. We aimed to rectify this by monitoring daily changes in cortical activity in the nonanesthetized mouse, an important preclinical model of disease and development. At ages approximately equivalent to normal human term birth, mouse cortex exhibits primarily network silence, with spontaneous “spindle bursts” as the only form of activity. In contrast, mature cortex is noisy, alternating between asynchronous/discontinuous and synchronous/continuous states. This work identifies the key processes that produce this maturation and provides a normative reference for murine-based studies of cortical circuit development