최적에 가까운 타이밍 적응을 위해 치우친 데이터 레벨과 눈 경사 디텍터를 사용한 최대 눈크기추적 클럭 및 데이터 복원회로 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.이 논문에서는 최소-비트 비트 에러율 (BER)에 대한 최대 눈크기 추적 CDR (MET-CDR)의 설계가 제안되었다. 제안 된 CDR 은 최적의 샘플링 단계를 찾기 위해 반복 절차를 가진 BER 카운터 또는 아이 모니터가 필 요하지 않다. 에러 샘플러 출력에 가중치를 두어 더하여 얻은 치우친 데 이터 레벨 (biased dLev) 은 사전 커서 ISI(pre-cursor ISI) 의 정보도 고려한 눈 높이 정보를 추출한다. 델타 T 만큼의 시간 차이를 둔 지점에서 작동 하는 두 샘플러는 현재 눈 높이와 눈 기울기의 극성을 감지하고, 이 정보 를 통해 제안하는 CDR 은 눈 기울기가 0 이되는 최대 눈 높이로 수렴한 다. 측정 결과는 최대 눈 높이와 최소 BER 의 샘플링 위치가 잘 일치 함 을 보여준다. 28nm CMOS 공정으로 구현된 수신기 칩은 23.5dB 의 채널 손실이 있는 상태에서 26Gb/s 에서 동작 가능하다. 0.25UI 의 아이 오프닝 을 가지며, 87mW 의 파워를 소비한다.In this thesis, design of a maximum-eye-tracking CDR (MET-CDR) for minimum bit error rate (BER) is proposed. The proposed CDR does not require a BER coun-ter or an eye-opening monitor with any iterative procedure to find the near-optimal sampling phase. The biased data-level obtained from the weighted sum of error sampler outputs, UP and DN, extracts the actual eye height information in the presence of pre-cursor ISI. Two samplers operating on two slightly different tim-ings detect the current eye height and the polarity of the eye slope so that the CDR tracks the maximum eye height where the slope becomes zero. Measured results show that the sampling phase of the maximum eye height and that of the mini-mum BER match well. A prototype receiver fabricated in 28 nm CMOS process operates at 26 Gb/s with an eye-opening of 0.25 UI and consumes 87 mW while equalizing 23.5 dB of loss at 13 GHz.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VIII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 RECEIVER FRONT-END 5 2.1.1 CHANNEL 7 2.1.2 EQUALIZER 17 2.1.3 CDR 32 2.2 PRIOR ARTS ON CLOCK RECOVERY 39 2.2.1 BB-CDR 39 2.2.2 BER-BASED CDR 41 2.2.3 EOM-BASED CDR 44 2.3 CONCEPT OF THE PROPOSED CDR 47 CHAPTER 3 MAXIMUM-EYE-TRACKING CDR WITH BIASED DATA-LEVEL AND EYE SLOPE DETECTOR 49 3.1 OVERVIEW 49 3.2 DESIGN OF MET-CDR 50 3.2.1 EYE HEIGHT INFORMATION FROM BIASED DATA-LEVEL 50 3.2.2 EYE SLOPE DETECTOR AND ADAPTATION ALGORITHM 60 3.2.3 ARCHITECTURE AND IMPLEMENTATION 67 3.2.4 VERIFICATION OF THE ALGORITHM 71 3.2.5 ANALYSIS ON THE BIASED DATA-LEVEL 76 3.3 EXPANSION OF MET-CDR TO PAM4 SIGNALING 84 3.3.1 MET-CDR WITH PAM4 84 3.3.2 CONSIDERATIONS FOR PAM4 87 CHAPTER 4 MEASUREMENT RESULTS 89 CHAPTER 5 CONCLUSION 99 APPENDIX A MATLAB CODE FOR SIMULATING RECEIVER WITH MET-CDR 100 BIBLIOGRAPHY 105 초 록 113Docto

Design of High-Speed SerDes Transceiver for Chip-to-Chip Communications in CMOS Process

With the continuous increase of on-chip computation capacities and exponential growth of data-intensive applications, the high-speed data transmission through serial links has become the backbone for modern communication systems. To satisfy the massive data-exchanging requirement, the data rate of such serial links has been updated from several Gb/s to tens of Gb/s. Currently, the commercial standards such as Ethernet 400GbE, InfiniBand high data rate (HDR), and common electrical interface (CEI)-56G has been developing towards 40+ Gb/s. As the core component within these links, the transceiver chipset plays a fundamental role in balancing the operation speed, power consumption, area occupation, and operation range. Meanwhile, the CMOS process has become the dominant technology in modern transceiver chip fabrications due to its large-scale digital integration capability and aggressive pricing advantage. This research aims to explore advanced techniques that are capable of exploiting the maximum operation speed of the CMOS process, and hence provides potential solutions for 40+ Gb/s CMOS transceiver designs. The major contributions are summarized as follows. A low jitter ring-oscillator-based injection-locked clock multiplier (RILCM) with a hybrid frequency tracking loop that consists of a traditional phase-locked loop (PLL), a timing-adjusted loop, and a loop selection state-machine is implemented in 65-nm C-MOS process. In the ring voltage-controlled oscillator, a full-swing pseudo-differential delay cell is proposed to lower the device noise to phase noise conversion. To obtain high operation speed and high detection accuracy, a compact timing-adjusted phase detector tightly combined with a well-matched charge pump is designed. Meanwhile, a lock-loss detection and lock recovery is devised to endow the RILCM with a similar lock-acquisition ability as conventional PLL, thus excluding the initial frequency set- I up aid and preventing the potential lock-loss risk. The experimental results show that the figure-of-merit of the designed RILCM reaches -247.3 dB, which is better than previous RILCMs and even comparable to the large-area LC-ILCMs. The transmitter (TX) and receiver (RX) chips are separately designed and fab- ricated in 65-nm CMOS process. The transmitter chip employs a quarter-rate multi-multiplexer (MUX)-based 4-tap feed-forward equalizer (FFE) to pre-distort the output. To increase the maximum operating speed, a bandwidth-enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. The receiver chip employs a two-stage continuous-time linear equalizer (CTLE) as the analog front-end and integrates an improved clock data recovery to extract the sampling clocks and retime the incoming data. To automatically balance the jitter tracking and jitter suppression, passive low-pass filters with adaptively-adjusted bandwidth are introduced into the data-sampling path. To optimize the linearity of the phase interpolation, a time-averaging-based compensating phase interpolator is proposed. For equalization, a combined TX-FFE and RX-CTLE is applied to compensate for the channel loss, where a low-cost edge-data correlation-based sign zero-forcing adaptation algorithm is proposed to automatically adjust the TX-FFE’s tap weights. Measurement results show that the fabricated transmitter/receiver chipset can deliver 40 Gb/s random data at a bit error rate of 16 dB loss at the half-baud frequency, while consuming a total power of 370 mW

Adaptive Receiver Design for High Speed Optical Communication

Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consuming power. In big data centers, the overall utilization ratio of IO links is less than 10%, corresponding to a large amount of energy wasted for idle operation. This work demonstrates a 60 Gb/s high sensitivity non-return-to-zero (NRZ) optical receiver in 14 nm FinFET technology with less than 7 ns power-on time. The power on time includes the data detection, analog bias settling, photo-diode DC current cancellation, and phase locking by the clock and data recovery circuit (CDR). The receiver autonomously detects the data demand on the link via a proposed link protocol and does not require any external enable or disable signals. The proposed link protocol is designed to minimize the off-state power consumption and power-on time of the link. In order to achieve high data-rate and high-sensitivity while maintaining the power budget, a 1-tap decision feedback equalization method is applied in digital domain. The sensitivity is measured to be -8 dBm, -11 dBm, and -13 dBm OMA (optical modulation amplitude) at 60 Gb/s, 48 Gb/s, and 32 Gb/s data rates, respectively. The energy efficiency in always-on mode is around 2.2 pJ/bit for all data-rates with the help of supply and bias scaling. The receiver incorporates a phase interpolator based clock-and-data recovery circuit with approximately 80 MHz jitter-tolerance corner frequency, thanks to the low-latency full custom CDR logic design. This work demonstrates the fastest ever reported CMOS optical receiver and runs almost at twice the data-rate of the state-of-the-art CMOS optical receiver by the time of the publication. The data-rate is comparable to BiCMOS optical receivers but at a fraction of the power consumption

차세대 자동차용 카메라 데이터 통신을 위한 비대칭 동시 양방향 송수신기의 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.본 학위 논문에서는 차세대 자동차용 카메라 링크를 위해 높은 속도의 4레벨 펄스 진폭 변조 신호와 낮은 속도의 2레벨 펄스 진폭 변조 신호를 통신하는 비대칭 동시 양방향 송수신기의 설계 기술에 대해 제안하고 검증되었다. 첫번째 프로토타입 설계에서는, 10B6Q 직류 밸런스 코드를 탑재한 4레벨 펄스 진폭 변조 송신기와 고정된 데이터와 참조 레벨을 가지는 4레벨 펄스 진폭 변조 적응형 수신기에 대한 내용이 기술되었다. 4레벨 펄스 진폭 변조 송신기에서는 교류 연결 링크 시스템에 대응하기 위한 면적 및 전력 효율성이 좋은 10B6Q 코드가 제안되었다. 이 코드는 직류 밸런스를 맞추고 연속적으로 같은 심볼을 가지는 길이를 6개로 제한 시킨다. 비록 여기서는 입력 데이터 길이 10비트를 사용하였지만, 제안된 기술은 카메라의 다양한 데이터 타입에 대응할 수 있도록 입력 데이터 길이에 대한 확장성을 가진다. 반면, 4레벨 펄스 진폭 변조 적응형 수신기에서는, 샘플러의 옵셋을 최적으로 제거하여 더 낮은 비트에러율을 얻기 위해서, 기존의 데이터 및 참조 레벨을 조절하는 대신, 이 레벨들은 고정시키고 가변 게인 증폭기를 적응형으로 조절하도록 하였다. 상기 10B6Q 코드 및 고정 데이터 및 참조레벨 기술을 가진 프로토타입 칩들은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었고 칩 온 보드 형태로 평가되었다. 10B6Q 코드는 합성 게이트 숫자는 645개와 함께 단 0.0009 mm2 의 면적 만을 차지한다. 또한, 667 MHz 동작 주파수에서 단 0.23 mW 의 전력을 소모한다. 10B6Q 코드를 탑재한 송신기에서 8-Gb/s 4레벨 펄스 진폭 변조 신호를 고정 데이터 및 참조 레벨을 가지는 적응형 수신기로 12-m 케이블 (22-dB 채널 로스) 을 통해서 보낸 결과 최소 비트 에러율 108 을 달성하였고, 비트 에러율 105 에서는 아이 마진이 0.15 UI x 50 mV 보다 크게 측정되었다. 송수신기를 합친 전력 소모는 65.2 mW (PLL 제외) 이고, 성과의 대표수치는 0.37 pJ/b/dB 를 보여주었다. 첫번째 프로토타입 설계을 포함하여 개선된 두번째 프로토타입 설계에서는, 12-Gb/s 4레벨 펄스 진폭 변조 정방향 채널 신호와 125-Mb/s 2레벨 펄스 진폭 변조 역방향 채널 신호를 탑재한 비대칭 동시 양방향 송수신기에 대해 기술되고 검증되었다. 제안된 넓은 선형 범위를 가지는 하이브리드는 gmC 저대역 통과 필터와 에코 제거기와 함께 아웃바운드 신호를 24 dB 이상 효율적으로 감소시켰다. 또한, 넓은 선형 범위를 가지는 하이브리드와 함께 게인 감소기를 형성하게 되는 선형 범위 증폭기를 통해 4레벨 펄스 진폭 변조 신호의 선형성과 진폭의 트레이드 오프 관계를 깨는 것이 가능하였다. 동시 양방향 송수신기 칩은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었다. 상기 설계 기술들을 이용하여, 4레벨 펄스 진폭 변조 및 2레벨 펄스 진폭 변조 송수신기 모두 5m 채널 (채널 로스 15.9 dB) 에서 1E-12 보다 낮은 비트 에러율을 달성하였고, 총 78.4 mW 의 전력 소모를 기록하였다. 종합적인 송수신기는 성과 대표지표로 0.41 pJ/b/dB 와 함께 동시 양방향 통신 아래에서 4레벨 펄스 진폭 변조 신호 및 2레벨 펄스 진폭 변조 신호 각각에서 아이 마진 0.15 UI 와 0.57 UI 를 달성하였다. 이 수치는 성과 대표지표 0.5 이하를 가지는 기존 동시 양방향 송수신기와의 비교에서 최고의 아이 마진을 기록하였다.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 초 록 106박

Analog Baseband Filters and Mixed Signal Circuits for Broadband Receiver Systems

Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems. The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation). High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented. Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers. The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology

Design of clock and data recovery circuits for energy-efficient short-reach optical transceivers

Nowadays, the increasing demand for cloud based computing and social media services mandates higher throughput (at least 56 Gb/s per data lane with 400 Gb/s total capacity 1) for short reach optical links (with the reach typically less than 2 km) inside data centres. The immediate consequences are the huge and power hungry data centers. To address these issues the intra-data-center connectivity by means of optical links needs continuous upgrading. In recent years, the trend in the industry has shifted toward the use of more complex modulation formats like PAM4 due to its spectral efficiency over the traditional NRZ. Another advantage is the reduced number of channels count which is more cost-effective considering the required area and the I/O density. However employing PAM4 results in more complex transceivers circuitry due to the presence of multilevel transitions and reduced noise budget. In addition, providing higher speed while accommodating the stringent requirements of higher density and energy efficiency (< 5 pJ/bit), makes the design of the optical links more challenging and requires innovative design techniques both at the system and circuit level. This work presents the design of a Clock and Data Recovery Circuit (CDR) as one of the key building blocks for the transceiver modules used in such fibreoptic links. Capable of working with PAM4 signalling format, the new proposed CDR architecture targets data rates of 50−56 Gb/s while achieving the required energy efficiency (< 5 pJ/bit). At the system level, the design proposes a new PAM4 PD which provides a better trade-off in terms of bandwidth and systematic jitter generation in the CDR. By using a digital loop controller (DLC), the CDR gains considerable area reduction with flexibility to adjust the loop dynamics. At the circuit level it focuses on applying different circuit techniques to mitigate the circuit imperfections. It presents a wideband analog front end (AFE), suitable for a 56 Gb/s, 28-Gbaud PAM-4 signal, by using an 8x interleaved, master/ slave based sample and hold circuit. In addition, the AFE is equipped with a calibration scheme which corrects the errors associated with the sampling channels’ offset voltage and gain mismatches. The presented digital to phase converter (DPC) features a modified phase interpolator (PI), a new quadrature phase corrector (QPC) and multi-phase output with de-skewing capabilities.The DPC (as a standalone block) and the CDR (as the main focus of this work) were fabricated in 65-nm CMOS technology. Based on the measurements, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Although the CDR was not fully operational with the PAM4 input, the results from 25-Gbaud PAM2 (NRZ) test setup were used to estimate the performance. Under this scenario, the 1-UI JTOL bandwidth was measured to be 2 MHz with BER threshold of 10−4. The chip consumes 236 mW of power while operating on 1 − 1.2 V supply range achieving an energyefficiency of 4.27 pJ/bit

Power-Proportional Optical Links

The continuous increase in data transfer rate in short-reach links, such as chip-to-chip and between servers within a data-center, demands high-speed links. As power efficiency becomes ever more important in these links, power-efficient optical links need to be designed. Power efficiency in a link can be achieved by enabling power-proportional communication over the serial link. In power-proportional links, the power dissipated by a link is proportional to the amount of data communicated. Normally, data-rate demand is not constant, and the peak data-rate is not required all the time. If a link is not adapted according to the data-rate demand, there will be a fixed power dissipation, and the power efficiency of the link will degrade during the sub-maximal link utilization. Adapting links to real-time data-rate requirements reduces power dissipation. Power proportionality is achieved by scaling the power of the serial link linearly with the link utilization, and techniques such as variable data-rate and burst-mode can be adopted for this purpose. Links whose data rate (and hence power dissipation) can be varied in response to system demands are proposed in this work. Past works have presented rapidly reconfigurable bandwidth in variable data-rate receivers, allowing lower power dissipation for lower data-rate operation. However, maintaining synchronization during reconfiguration was not possible since previous approaches have introduced changes in front-end delay when they are reconfigured. This work presents a technique that allows rapid bandwidth adjustment while maintaining a near-constant delay through the receiver suitable for a power-scalable variable data-rate optical link. Measurements of a fabricated integrated circuit (IC) show nearly constant energy per bit across a 2× variation in data rate while introducing less than 10 % of a unit interval (UI) of delay variation. With continuously increasing data communication in data-centers, parallel optical links with ever-increasing per-lane data rates are being used to meet overall throughput demands. Simultaneously, power efficiency is becoming increasingly important for these links since they do not transmit useful data all the time. The burst-mode solution for vertical-cavity surface-emitting laser (VCSEL)-based point-to-point communication can be used to improve links’ energy efficiency during low link activity. The burst-mode technique for VCSEL-based links has not yet been deployed commercially. Past works have presented burst-mode solutions for single-channel receivers, allowing lower power dissipation during low link activity and solutions for fast activation of the receivers. However, this work presents a novel technique that allows rapid activation of a front-end and fast locking of a clock-and-data-recovery (CDR) for a multi-channel parallel link, utilizing opportunities arising from the parallel nature of many VCSEL-based links. The idea has been demonstrated through electrical and optical measurements of a fabricated IC at 10 Gbps, which show fast data detection and activation of the circuitry within 49 UIs while allowing the front-end to achieve better energy efficiency during low link activity. Simulation results are also presented in support of the proposed technique which allows the CDR to lock within 26 UIs from when it is powered on

Toward realizing power scalable and energy proportional high-speed wireline links

Growing computational demand and proliferation of cloud computing has placed high-speed serial links at the center stage. Due to saturating energy efficiency improvements over the last five years, increasing the data throughput comes at the cost of power consumption. Conventionally, serial link power can be reduced by optimizing individual building blocks such as output drivers, receiver, or clock generation and distribution. However, this approach yields very limited efficiency improvement. This dissertation takes an alternative approach toward reducing the serial link power. Instead of optimizing the power of individual building blocks, power of the entire serial link is reduced by exploiting serial link usage by the applications. It has been demonstrated that serial links in servers are underutilized. On average, they are used only 15% of the time, i.e. these links are idle for approximately 85% of the time. Conventional links consume power during idle periods to maintain synchronization between the transmitter and the receiver. However, by powering-off the link when idle and powering it back when needed, power consumption of the serial link can be scaled proportionally to its utilization. This approach of rapid power state transitioning is known as the rapid-on/off approach. For the rapid-on/off to be effective, ideally the power-on time, off-state power, and power state transition energy must all be close to zero. However, in practice, it is very difficult to achieve these ideal conditions. Work presented in this dissertation addresses these challenges. When this research work was started (2011-12), there were only a couple of research papers available in the area of rapid-on/off links. Systematic study or design of a rapid power state transitioning in serial links was not available in the literature. Since rapid-on/off with nanoseconds granularity is not a standard in any wireline communication, even the popular test equipment does not support testing any such feature, neither any formal measurement methodology was available. All these circumstances made the beginning difficult. However, these challenges provided a unique opportunity to explore new architectural techniques and identify trade-offs. The key contributions of this dissertation are as follows. The first and foremost contribution is understanding the underlying limitations of saturating energy efficiency improvements in serial links and why there is a compelling need to find alternative ways to reduce the serial link power. The second contribution is to identify potential power saving techniques and evaluate the challenges they pose and the opportunities they present. The third contribution is the design of a 5Gb/s transmitter with a rapid-on/off feature. The transmitter achieves rapid-on/off capability in voltage mode output driver by using a fast-digital regulator, and in the clock multiplier by accurate frequency pre-setting and periodic reference insertion. To ease timing requirements, an improved edge replacement logic circuit for the clock multiplier is proposed. Mathematical modeling of power-on time as a function of various circuit parameters is also discussed. The proposed transmitter demonstrates energy proportional operation over wide variations of link utilization, and is, therefore, suitable for energy efficient links. Fabricated in 90nm CMOS technology, the voltage mode driver, and the clock multiplier achieve power-on-time of only 2ns and 10ns, respectively. This dissertation highlights key trade-off in the clock multiplier architecture, to achieve fast power-on-lock capability at the cost of jitter performance. The fourth contribution is the design of a 7GHz rapid-on/off LC-PLL based clock multi- plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita- tions of the MDLL based approach. Proposed temperature compensated LC-PLL achieves power-on-lock in 1ns. The fifth and biggest contribution of this dissertation is the design of a 7Gb/s embedded clock transceiver, which achieves rapid-on/off capability in LC-PLL, current-mode transmit- ter and receiver. It was the first reported design of a complete transceiver, with an embedded clock architecture, having rapid-on/off capability. Background phase calibration technique in PLL and CDR phase calibration logic in the receiver enable instantaneous lock on power-on. The proposed transceiver demonstrates power scalability with a wide range of link utiliza- tion and, therefore, helps in improving overall system efficiency. Fabricated in 65nm CMOS technology, the 7Gb/s transceiver achieves power-on-lock in less than 20ns. The transceiver achieves power scaling by 44x (63.7mW-to-1.43mW) and energy efficiency degradation by only 2.2x (9.1pJ/bit-to-20.5pJ/bit), when the effective data rate (link utilization) changes by 100x (7Gb/s-to-70Mb/s). The sixth and final contribution is the design of a temperature sensor to compensate the frequency drifts due to temperature variations, during long power-off periods, in the fast power-on-lock LC-PLL. The proposed self-referenced VCO-based temperature sensor is designed with all digital logic gates and achieves low supply sensitivity. This sensor is suitable for integration in processor and DRAM environments. The proposed sensor works on the principle of directly converting temperature information to frequency and finally to digital bits. A novel sensing technique is proposed in which temperature information is acquired by creating a threshold voltage difference between the transistors used in the oscillators. Reduced supply sensitivity is achieved by employing junction capacitance, and the overhead of voltage regulators and an external ideal reference frequency is avoided. The effect of VCO phase noise on the sensor resolution is mathematically evaluated. Fabricated in the 65nm CMOS process, the prototype can operate with a supply ranging from 0.85V to 1.1V, and it achieves a supply sensitivity of 0.034oC/mV and an inaccuracy of ±0.9oC and ±2.3oC from 0-100oC after 2-point calibration, with and without static nonlinearity correction, respectively. It achieves a resolution of 0.3oC, resolution FoM of 0.3(nJ/conv)res2 , and measurement (conversion) time of 6.5μs

Design and applications of advanced optical modulation formats for optical metro/access transmission systems.

光纖通信技術與光網絡在過去三十年間極大地改變了人們的生活。雖然整個光通信行業因為2000年互聯網泡沫的破滅受到了影響，但近年來由於高清電視，移動多媒體和社交網絡的興盛，互聯網對通信網絡傳輸帶寬的需求達到了前所未有的高度，進而推動了光通信行業的再一次興盛。站在行業的高度來看，寬帶接入網無疑是推動行業發展的最主要領域。而實現寬帶接入網的最主要技術則是無源光網絡技術。無源光網絡的本質是一個樹型拓撲的光網絡，其主要的傳輸光纖可被多用戶共享，且在中央基站和用戶之間無任何有源器件，從而大大降低了網絡的成本。然而，在具體實踐中，仍然有許多的技術難題需要解決，例如：無色光網絡單元、突發性傳輸、全雙工傳輸、長距離無源光網絡和網絡功能集成等。這些技術需求亦反應了市場對通信技術發展的要求，及“更快，更便宜，更灵活“。為滿足無源光網絡的技術要求，研究者們從不同的角度提出了各種解決方案，研究領域囊括光傳輸技術、新型器件、系統結構、網絡協議等等。本論文研究從傳輸碼型的角度來解決上述一項或幾項問題。研究碼型包括雙二進制反歸零碼，雙二進制曼切斯特碼，還有常規曼切斯特碼。研究內容則包括上述碼型的產生、接收、傳輸特性和系統應用等等。論文首貳章為概要和背景技術介紹，其餘幾章則按照不同的碼型分類討論。本論文第一項研究課題為雙二進制反歸零碼。相比傳統的歸零碼和反歸零碼，雙二進制反歸零碼具有更大的色散容限，且每個傳輸符號均有能量。我們先研究了它的優勢，調製/解調方法，而後研究了該碼型在無源光網絡中的具體應用，包括10‐Gb/s 全光組播系統和基於重調製的80 公里長距離波分複用無源光網絡系統。第二項研究課題為雙二進制曼切斯特碼型，該碼型的優勢包括較大的時鐘分量，窄帶寬，無直流分量等。我們提出了一種基於直接調製的雙二進制曼切斯特碼產生方法。該方法具有高效，低價，高輸出功率等特點。基於該雙二進制曼切斯特碼發射機，我們實現了70 公里雙向傳輸的波分複用無源光網絡。該系統下行傳輸採用雙二進制曼切斯特碼型，上行傳輸採用直接調製的反射式半導體激光器，所以系統成本大大降低。最後，我們研究了電色散補償技術對於傳統曼切斯特碼型的傳輸性能的改善。所使用的電均衡技術包括前向均衡器、判決反饋均衡器和極大似然估計均衡器。通過離線處理的方法，我們對曼切斯特碼型在三種均衡器下的傳輸性能進行了實驗驗證。研究內容包括前向均衡器和判決反饋均衡器抽頭數的優化、不同採樣率下系統性能、極大似然估計中狀態機個數的影響和不同的曼切斯特接收機的影響等等。The increasing demands for bandwidth have aroused a myriad of industry and academic activities in developing high-speed and cost-effective optical networks,among which optical broad band access networks was the main driving force for such growth in recent years. The most promising solution to optical broadband access network is the passive optical network (PON), which is a point-to-multipoint tree-topology network that connects optical line terminal (OLT) with many optical network units (ONUs) via a long fiber feeder and many short distribution fibers. Promising the concept it is, it raises many detailed technical challenges, such as colorless ONUs, burst mode transmission, bi-directional transmission with mitigated backscattering noise, long-reach PON, and integrating network functionalities. All of the technical requirements are motivated by the “original requirements“ of telecommunication -- faster, cheaper, and more robust.To fulfill the technical requirements, different researchers take different angles to design system and to study the enabling technologies. For example, devices, system architectures, network protocols, etc. In this thesis research, we have tried to deal with one or multiple problems by employing advanced modulation formats for the optical signals. In particular, we have studied IRZ-duobinary, Manchester-duobinary, and Manchester formats, including the modulation/demodulation techniques, transmission properties, and system applications. The research topics are classified according to the type of modulation formats.In the first topic, IRZ-duobinary format is proposed for optical signal transmission. It has desirable properties of large dispersion tolerance (as compared to conventional RZ/IRZ) and finite optical power in each bit. In this study, we firstly show the advantages of IRZ-duobinary and the corresponding modulation techniques. Then, we demonstrate a 10-Gb/s per channel optical multicast overlay scheme and an 80-km-reach system with re-modulated ONU, both in wavelength division multiplexing (WDM) PON.In the second topic, Manchester-duobinary format, which has the advantages including easy clock/level recovery, compressed bandwidth, and zero DC component, is studied. We propose an efficient and cost-effective Manchester-duobinary transmitter by properly modulating a chirp managed laser (CML) with electrical Manchester signal. Then, a cost-effective CLS 70-km-Reach full-duplex WDM-PON with downstream 10-Gb/s Manchester-duobinary signal and upstream 1.25-Gb/s re-modulated NRZ-OOK signal is proposed and experimentally demonstrated. This design simultaneously solves the problems of colorless ONU, bi-directional transmission, and long-reach, using cost-effective system design and devices.Finally, we investigate the performance of electronic dispersion compensation (EDC) technique on 10-Gb/s Manchester coded optical signal, so as to further improve its dispersion tolerance and may enables its applications in long-reach PON. In this study, feed forward equalizer (FFE), decision feedback equalizer (DFE), and maximum-likelihood sequence estimation (MLSE) are employed as the equalizers Utilizing off-line signal processing, the performance of different equalizers with different parameters (number of taps, sampling rates, number of states, etc.) under both cases of single-ended and balanced detection are studied and compared. Experimental results show that the transmission distance of Manchester coded signal can be increased by a factor of three with four-sample-per-symbol FFE-DFE.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Liu, Zhixin.Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.Includes bibliographical references (leaves 128-148).Abstract also in Chinese.Acknowledgement --- p.1Abstract --- p.3摘要 --- p.5Table of contents --- p.7List of figures and tables --- p.13Chapter Chapter 1. --- IntroductionChapter 1.1 --- Optical Broadband Access --- p.18Chapter 1.1.1 --- Bandwidth requirement --- p.19Chapter 1.1.2 --- Passive optical networks --- p.22Chapter 1.2 --- Research Challenge of Next-Generation Optical Access Network --- p.25Chapter 1.2.1 --- Colorless ONU --- p.25Chapter 1.2.2 --- Burst Mode Transmission --- p.27Chapter 1.2.3 --- Backscattering Noise in PON --- p.28Chapter 1.2.4 --- Long-Reach Access Network --- p.30Chapter 1.2.5 --- Enriching Network Functionalities --- p.31Chapter 1.3 --- Major contribution of this thesis --- p.32Chapter 1.3.1 --- IRZ-duobinary transmitter and application --- p.32Chapter 1.3.2 --- Manchester-duobinary transmitter and application --- p.33Chapter 1.3.3 --- Receiver with electronic equalizer for Manchester signal --- p.34Chapter 1.4 --- Outline of this Thesis --- p.35Chapter Chapter 2. --- Optical Modulation Technique and Transmission ImpairmentsChapter 2.1 --- Optical Modulation techniques --- p.38Chapter 2.1.1 --- Chirp managed laser --- p.38Chapter 2.1.2 --- Mach-Zehnder modulator --- p.41Chapter 2.2 --- Transmission Impairments --- p.47Chapter 2.2.1 --- Noise --- p.47Chapter 2.2.2 --- Chromatic dispersion --- p.49Chapter 2.2.3 --- Fiber nonlinearity --- p.50Chapter 2.3 --- Impairment Mitigation Techniques --- p.51Chapter 2.3.1 --- In-line compensation techniques --- p.51Chapter 2.3.2 --- Post-compensation techniques --- p.52Chapter Chapter 3. --- Optical Multicast and Re-modulation Based on Inverse-RZ-duobinary TransmitterChapter 3.1 --- Introduction --- p.53Chapter 3.2 --- IRZ-duobinary transmitter --- p.55Chapter 3.2.1 --- Generation of IRZ-duobinary format --- p.55Chapter 3.2.2 --- Comparison of different configurations of IRZ-duobinary generation --- p.56Chapter 3.3 --- IRZ-duobinary format for optical multicast in WDM-PON --- p.60Chapter 3.3.1 --- Optical multicast in WDM-PON --- p.60Chapter 3.3.2 --- Proposed system architecture --- p.61Chapter 3.3.3 --- Experimental demonstration of the proposed optical multicast system --- p.65Chapter 3.4 --- IRZ-duobinary for long-reach PON --- p.68Chapter 3.4.1 --- Long-reach PON using DI based IRZ-duobinary transmitter --- p.69Chapter 3.4.2 --- Long-reach PON using CML based IRZ-duobinary transmitter --- p.75Chapter 3.5 --- Summary --- p.81Chapter Chapter 4. --- Manchester-duobinary Transmitter for Bi-directional WDM-PONChapter 4.1 --- Introduction --- p.83Chapter 4.2 --- Manchester-duobinary transmitter --- p.85Chapter 4.2.1 --- Mach-Zehnder modulator based Manchester-duobinary transmitter --- p.85Chapter 4.2.2 --- Chirp managed laser based Manchester-duobinary transmitter --- p.87Chapter 4.3 --- Rayleigh noise mitigated bi-directional WDM-PON based on Manchester-duobinary transmitter --- p.94Chapter 4.3.1 --- CLS Bi-directional long-reach WDM-PON. --- p.94Chapter 4.3.2 --- Proposed system architecture --- p.97Chapter 4.3.3 --- Experimental demonstration --- p.99Chapter 4.4 --- Summary --- p.102Chapter Chapter 5. --- Electronic Equalizer for Manchester Coded SignalChapter 5.1 --- Introduction --- p.103Chapter 5.2 --- Electronic equalizer for CD compensation --- p.104Chapter 5.2.1 --- Channel model --- p.104Chapter 5.2.2 --- FFE-DFE --- p.106Chapter 5.2.3 --- MLSE --- p.107Chapter 5.3 --- FFE-DFE for Manchester signal --- p.109Chapter 5.3.1 --- Experimental setup for CD compensation of Manchester signal using FFE-DFE --- p.110Chapter 5.3.2 --- Results and discussion --- p.112Chapter 5.4 --- MLSE equalizer for Manchester signal --- p.121Chapter 5.4.1 --- Experimental setup for CD compensation of Manchester format using MLSE --- p.121Chapter 5.4.1 --- Results and discussion --- p.122Chapter 5.5 --- Summary --- p.124Chapter Chapter 6. --- ConclusionChapter 6.1 --- Summary of this thesis --- p.125Chapter 6.2 --- Future work --- p.127References --- p.128Chapter Appendix: --- p.149Chapter A. --- List of abbreviations --- p.149Chapter B. --- List of publications --- p.15