Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Enhancement of Exon Regions Recognition in Gene Sequences Using a Radix -4 Multi-valued Logic with DSP Approach

Numerous levels of concepts perform logical designand logical representations in an efficient manner. In typical and quantum theories of computation, Binary logic and Boolean algebra occupies an imperative place. But they havethe limitation of representing signals or sequences by using either binary ‘1’ or ‘0’. This has major drawbacks that the neutralities or any intermediate values are ignored which are essential in most of the applications. Because of the occurrence of such situations it is the need of the hour to look into other alternative logics in order to fulfill the necessities of the user in their respective applications. The binary logic can be replaced by Multi-Valued Logic (MVL), which grabs the positions of the major applications because of the ability to provide representation by using more than two values.As most of the significant applications are based on the logical sequences, the multi-valued logic shines because of its thriving feature. Genomic signal processing, a novel research area in bioinformatics,is one of the foremost applications which involve the operations of logical sequences. It is concerned with the digital signal representations and analysis of genomic data.Determination of the coding region in DNA sequence is one of the genomic operations.This leads to the identification of the characteristics of the gene which in turn finds out an individual’s behavior. In order to extract the coding regions on the basis of logical sequences a number of techniques have been proposed by researchers. But most of the works utilized binary logic, which lead to the problem of losing some of the coding regions and incorrectly recognizing non-coding regions as the coding regions. Hereby,we are proposing an approach for recognizing the exon regions from a gene sequence based on the multi-valued logic. In this approach, we have utilized fourlevel logical system, termed as quaternary logic for the representation of gene sequences and so that we recognize theexon regions from the DNA sequence

A comparison of processing techniques for producing prototype injection moulding inserts.

This project involves the investigation of processing techniques for producing low-cost moulding inserts used in the particulate injection moulding (PIM) process. Prototype moulds were made from both additive and subtractive processes as well as a combination of the two. The general motivation for this was to reduce the entry cost of users when considering PIM. PIM cavity inserts were first made by conventional machining from a polymer block using the pocket NC desktop mill. PIM cavity inserts were also made by fused filament deposition modelling using the Tiertime UP plus 3D printer. The injection moulding trials manifested in surface finish and part removal defects. The feedstock was a titanium metal blend which is brittle in comparison to commodity polymers. That in combination with the mesoscale features, small cross-sections and complex geometries were considered the main problems. For both processing methods, fixes were identified and made to test the theory. These consisted of a blended approach that saw a combination of both the additive and subtractive processes being used. The parts produced from the three processing methods are investigated and their respective merits and issues are discussed

Reducing risk in pre-production investigations through undergraduate engineering projects.

This poster is the culmination of final year Bachelor of Engineering Technology (B.Eng.Tech) student projects in 2017 and 2018. The B.Eng.Tech is a level seven qualification that aligns with the Sydney accord for a three-year engineering degree and hence is internationally benchmarked. The enabling mechanism of these projects is the industry connectivity that creates real-world projects and highlights the benefits of the investigation of process at the technologist level. The methodologies we use are basic and transparent, with enough depth of technical knowledge to ensure the industry partners gain from the collaboration process. The process we use minimizes the disconnect between the student and the industry supervisor while maintaining the academic freedom of the student and the commercial sensitivities of the supervisor. The general motivation for this approach is the reduction of the entry cost of the industry to enable consideration of new technologies and thereby reducing risk to core business and shareholder profits. The poster presents several images and interpretive dialogue to explain the positive and negative aspects of the student process

Circuit-level modelling and simulation of carbon nanotube devices

The growing academic interest in carbon nanotubes (CNTs) as a promising novel class of electronic materials has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. Together with the increasing amount of theoretical analysis and experimental studies into the properties of CNT transistors, the need for corresponding modelling techniques has also grown rapidly. This research is focused on the electron transport characteristics of CNT transistors, with the aim to develop efficient techniquesto model and simulate CNT devices for logic circuit analysis.The contributions of this research can be summarised as follows. Firstly, to accelerate the evaluation of the equations that model a CNT transistor, while maintaining high modelling accuracy, three efficient numerical techniques based on piece-wise linear, quadratic polynomial and cubic spline approximation have been developed. The numerical approximation simplifies the solution of the CNT transistor’s self-consistent voltage such that the calculation of the drain-source current is accelerated by at least two orders of magnitude. The numerical approach eliminates complicated calculations in the modelling process and facilitates the development of fast and efficient CNT transistor models for circuit simulation.Secondly, non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomena, including elastic scattering, phonon scattering, strain and tunnelling effects, have been developed. A salient feature of the developed models is their ability to incorporate both ballistic and non-ballistic transport mechanisms without a significant computational cost. The developed models have been extensively validated against reported transport theories of CNT transistors and experimental results.Thirdly, the proposed carbon nanotube transistor models have been implemented on several platforms. The underlying algorithms have been developed and tested in MATLAB, behaviourallevel models in VHDL-AMS, and improved circuit-level models have been implemented in two versions of the SPICE simulator. As the final contribution of this work, parameter variation analysis has been carried out in SPICE3 to study the performance of the proposed circuit-level CNT transistor models in logic circuit analysis. Typical circuits, including inverters and adders, have been analysed to determine the dependence of the circuit’s correct operation on CNT parameter variation