Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

A Robust 43-GHz VCO in CMOS for OC-768 SONET Applications

In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used

Design of a 4.2-5.4 GHz differential LC VCO using 0.35 mu m SiGeBiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2-5.4 GHz, -Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 mu m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is -110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and -113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm(2) on Si substrate, including DC and RF pads

Design of a 4.2-5.4 GHz Differential LC VCO using 0.35 m SiGe BiCMOS Technology

In this paper, a 4.2-5.4 GHz, Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35´m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). Phase noise is -110.7 dBc/Hz at 1MHz offset from 5.4 GHz carrier frequency and -113.5 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained utilizing accumulation-mode varactors. Phase noise is relatively low due to taking the advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. The circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit occupies an area of 0.6 mm2 on Si substrate including RF and DC pads

A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators

© 2017 World Scientific Publishing Company.In this work, a novel circuit structure for second-harmonic multi-phase voltage controlled oscillator (MVCO) is presented. The proposed MVCO is composed of (Formula presented.) ((Formula presented.) being an integer number and (Formula presented.)2) identical inductor–capacitor ((Formula presented.)) tank VCOs. In theory, this MVCO can provide 2(Formula presented.) different phase sinusoidal signals. A six-phase VCO based on the proposed structure is designed in a TSMC 0.18(Formula presented.)um CMOS process. Simulation results show that at the supply voltage of 0.8(Formula presented.)V, the total power consumption of the six-phase VCO circuit is about 1(Formula presented.)mW, the oscillation frequency is tunable from 2.3(Formula presented.)GHz to 2.5(Formula presented.)GHz when the control voltage varies from 0(Formula presented.)V to 0.8(Formula presented.)V, and the phase noise is lower than (Formula presented.)128(Formula presented.)dBc/Hz at 1(Formula presented.)MHz offset frequency. The proposed MVCO has lower phase noise, lower power consumption and more outputs than other related works in the literature.Peer reviewedFinal Accepted Versio

Quadrature LC VCO with passive coupling and phase combining network

A circuit and method for generating a signal is disclosed. The circuit includes a set of wide tuning LC tanks, a set of core transistors cross coupled to the set of wide tuning LC tanks, and a combining network coupled to the set of wide tuning LC tanks and the set of core transistors. The combining network further includes a set of inputs connected to the set of wide tuning LC tanks and the set of core transistors, a set of coupling transistors connected to the set of inputs, a set of source inductors connected to the set of coupling transistors, a coupling capacitor connected to the set of source inductors, a load resistor connected to the coupling capacitor. The combining network combines the set of inputs and the signal is delivered to the load resistor as a fourth order harmonic.Board of Regents, University of Texas Syste

A 4.5-5.8 GHz Differential LC VCO using 0.35 m SiGe BiCMOS Technology

In this paper, design and realization of a 4.5-5.8 GHz, Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is implemented with 0.35´m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). A linear, 1300 MHz tuning range is measured with accumulation-mode varactors. Fundamental frequency output power changes between -1.6 dBm and 0.9 dBm, depending on the tuning voltage. The circuit draws 17 mA from 3.3 V supply, including buffer circuits leading to a total power dissipation of 56 mW. Post-layout phase noise is simulated -110.7 dBc/Hz at 1MHz offset from 5.8 GHz carrier frequency and -113.4 dBc/Hz from 4.5 GHz carrier frequency. Phase noise measurements will be updated in the final manuscript. The circuit occupies an area of 0.6 mm2 on Si substrate including RF and DC pads

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer