Ultra-Low Power Circuit Design for Miniaturized IoT Platform

This thesis examines the ultra-low power circuit techniques for mm-scale Internet of Things (IoT) platforms. The IoT devices are known for their small form factors and limited battery capacity and lifespan. So, ultra-low power consumption of always-on blocks is required for the IoT devices that adopt aggressive duty-cycling for high power efficiency and long lifespan. Several problems need to be addressed regarding IoT device designs, such as ultra-low power circuit design techniques for sleep mode and energy-efficient and fast data rate transmission for active mode communication. Therefore, this thesis highlights the ultra-low power always-on systems, focusing on energy efficient optical transmission in order to miniaturize the IoT systems. First, this thesis presents a battery-less sub-nW micro-controller for an always-operating system implemented with a newly proposed logic family. Second, it proposes an always-operating sub-nW light-to-digital converter to measure instant light intensity and cumulative light exposure, which employs the characteristics of this proposed logic family. Third, it presents an ultra-low standby power optical wake-up receiver with ambient light canceling using dual-mode operation. Finally, an energy-efficient low power optical transmitter for an implantable IoT device is suggested. Implications for future research are also provided.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/145862/1/imhotep_1.pd

Ultra-Low Power Optical Interface Circuits for Nearly Invisible Wireless Sensor Nodes.

Technological advances in the semiconductor industry and integrated circuit design have resulted in electronic devices that are smaller and cheaper than ever, and yet they are more pervasive and powerful than what could hardly be imagined several decades ago. Nowadays, small hand-held devices such as smartphones have completely reshaped the way people communicate, share information, and get entertained. According to Bell’s Law, the next generation of computers will be cubic-millimeter-scale in volume with more prevalent presence than any other computing platform available today, opening up myriad of new applications. In this dissertation, a millimeter-scale wireless sensor node for visual sensing applications is proposed, with emphasis on the optical interface circuits that enable wireless optical communication and visual imaging. Visual monitoring and imaging with CMOS image sensors opens up a variety of new applications for wireless sensor nodes, ranging from surveillance to in vivo molecular imaging. In particular, the ability to detect motion can enable intelligent power management through on-demand duty cycling and reduce the data storage requirement. Optical communication provides an ultra-low power method to wirelessly control or transmit data to the sensor node after encapsulation and deployment. The proposed wireless sensor node is a nearly-invisible, yet a complete system with imaging, optics, two-way wireless communication, CPU, memory, battery and energy harvesting with solar cells. During its ultra-low power motion detection mode, the overall power consumption is merely 304 nW, allowing energy autonomous continuous operation with 10 klux of background lighting. Such complete features in the unprecedented form factor can revolutionize the role of electronics in our future daily lives, taking the “Smart Dust” concept from fiction to reality.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110399/1/coolkgh_1.pd

Ultra-Low Power Circuit Design for Cubic-Millimeter Wireless Sensor Platform.

Modern daily life is surrounded by smaller and smaller computing devices. As Bell’s Law predicts, the research community is now looking at tiny computing platforms and mm3-scale sensor systems are drawing an increasing amount of attention since they can create a whole new computing environment. Designing mm3-scale sensor nodes raises various circuit and system level challenges and we have addressed and proposed novel solutions for many of these challenges to create the first complete 1.0mm3 sensor system including a commercial microprocessor. We demonstrate a 1.0mm3 form factor sensor whose modular die-stacked structure allows maximum volume utilization. Low power I2C communication enables inter-layer serial communication without losing compatibility to standard I2C communication protocol. A dual microprocessor enables concurrent computation for the sensor node control and measurement data processing. A multi-modal power management unit allowed energy harvesting from various harvesting sources. An optical communication scheme is provided for initial programming, synchronization and re-programming after recovery from battery discharge. Standby power reduction techniques are investigated and a super cut-off power gating scheme with an ultra-low power charge pump reduces the standby power of logic circuits by 2-19× and memory by 30%. Different approaches for designing low-power memory for mm3-scale sensor nodes are also presented in this work. A dual threshold voltage gain cell eDRAM design achieves the lowest eDRAM retention power and a 7T SRAM design based on hetero-junction tunneling transistors reduces the standby power of SRAM by 9-19× with only 15% area overhead. We have paid special attention to the timer for the mm3-scale sensor systems and propose a multi-stage gate-leakage-based timer to limit the standard deviation of the error in hourly measurement to 196ms and a temperature compensation scheme reduces temperature dependency to 31ppm/°C. These techniques for designing ultra-low power circuits for a mm3-scale sensor enable implementation of a 1.0mm3 sensor node, which can be used as a skeleton for future micro-sensor systems in variety of applications. These microsystems imply the continuation of the Bell’s Law, which also predicts the massive deployment of mm3-scale computing systems and emergence of even smaller and more powerful computing systems in the near future.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91438/1/sori_1.pd

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT ) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time

The impact of supply voltage scaling on the retention time of a 2-transistor (2T) gain-cell (GC) storage array is investigated, in order to enable low-power/low-voltage data storage. The retention time can be increased when scaling down the supply voltage for a given access statistics and a given write bit-line (WBL) control scheme. Moreover, for a given supply voltage, the retention time can be further increased by controlling the WBL to a voltage level between the supply rails during idle and read states. These two concepts are proved by means of Spectre simulation of a GC-storage array implemented in 180-nm CMOS technology. The proposed 2-kb storage macro is operated at only 40% of the nominal supply voltage and leverages the GCs to enable two-port operation with a negligible area-increase compared to a single-port implementation

A fully integrated 2:1 self-oscillating switched-capacitor DC-DC converter in 28 nm UTBB FD-SOI

The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter’s large load power range and high efficiency make it an excellent fit for energy-constrained processors.</p

WIRELESS SENSOR NODE WITH LOW-POWER SENSING

Wireless sensor network consists of a large number of simply sensor nodes that collect information from the external environment by sensors, process the information, and communicate with other neighboring nodes in the network. Usually sensor nodes operate with exhaustible batteries unattended. Since manual replacement or recharging the batteries is not an easy, desirable and always possible task, the power consumption becomes a very important issue in the development of these networks. The total power consumption of a node is a result of all steps of operation: sensing, data processing and radio transmission. In this work we focus on the impact of sensing hardware on the total power consumption of a sensor node. Firstly, we describe the structure of sensor node architecture, identify its key energy consumption sources, and introduce an energy model for the sensing subsystem as building block of a node. Secondly, with aim to reduce energy consumption of a node we propose implementation of two power-saving techniques: duty-cycling and power-gating. Duty-cycling is effective at system level. It is used for switching a node between active and sleep mode (with duty-cycle factor of 1% reduction of in dynamic energy consumption is achieved). Power-gating is implemented at circuit level with goal to decrease a power loss due to leakage current (in our design, a reduction of dynamic and static energy consumption of off-chip sensor elements as constituents of sensing hardware within a node of is achieved). Our MATLAB simulation results suggest that in total for a sensing hardware thanks to involving of duty-cycling and power-gating secures a three order of magnitude reduction ( ) in energy consumption can be achieved compared to a node architecture in which the implementation of  both energy saving techniques are omitted

Design of Logic-Compatible Embedded Flash Memories for Moderate Density On-Chip Non-Volatile Memory Applications

University of Minnesota Ph.D. dissertation. December 2013. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); xx, 129 pages.An on-chip embedded NVM (eNVM) enables a zero-standby power system-on-a-chip with a smaller form factor, faster access speed, lower access power, and higher security than an off-chip NVM. Differently from the high density eNVM technologies such as dual-poly eflash, FeRAM, STT-MRAM, and RRAM that typically require process overhead beyond standard logic process, the moderate density eNVM technologies such as e-fuse, anti-fuse, and single-poly embedded flash (eflash) can be fabricated in a standard logic process with no process overhead. Among them, a single-poly eflash is a unique multiple-time programmable moderate density eNVM, while it is expected to play a key role in mitigating variability and reliability issues of the future VLSI technologies; however, the challenges such as a high voltage disturbance, an implementation of logic compatible High Voltage Switch (HVS), and a limited sensing margin are required to be solved for its implementation using a standard I/O device. This thesis focuses on alleviating such challenges of the single-poly eflash memory with three single-poly eflash designs proposed in a generic logic process for moderate density eNVM applications. Firstly, the proposed 5T eflash features a WL-by-WL accessible architecture with no disturbance issue of the unselected WL cells, an overstress-free multi-story HVS expanding the cell sensing margin, and a selective WL refresh scheme for the higher cell endurance. The most favorable eflash cell configuration is also studied when the performance, endurance, retention, and disturbance characteristics are all considered. Secondly, the proposed 6T eflash features the bit-by-bit re-write capability for the higher overall cell endurance, while not disturbing the unselected WL cells. The logic compatible on-chip charge pump to provide the appropriate high voltages for the proposed eflash operations is also discussed. Finally, the proposed 10T eflash features a multi-configurable HVS that does not require the boosted read supplies, and a differential cell architecture with improved retention time. All these proposed eflash memories were implemented in a 65nm standard logic process, and the test chip measurement results confirmed the functionality of the proposed designs with a reasonable retention margin, showing the competitiveness of the proposed eflash memories compared to the other moderate density eNVM candidates

Electromagnetic energy harvesting based on HfZrO tunneling junctions

HfZrO ferroelectrics with a thickness of 6 nm were grown directly on Si using atomic layer deposition, top and bottom metallic electrodes being subsequently deposited by electron-beam metallization techniques. Depending on the polarity of the ±10 V poling voltages, the current–voltage dependence of these tunneling diodes shows a rectifying behavior for different polarizations, the ON–OFF ratio being about 104. Because the currents are at mA level, the HfZrO tunneling diodes coupled to an antenna array can harvest electromagnetic energy at 26 GHz (a bandwidth designated for internet of things), with a responsivity of 63 V W−1 and a NEP of 4 nW/Hz0.5