Design of low-dropout regulator for ultra low power on-chip applications

Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture

Efficiency Improvement of LDO Output Based Linear Regulator With Supercapacitor Energy Recovery – A versatile new technique with an example of a 5V to 1.5V version

Supercapacitors are used in various industrial applications and the supercapacitors technology is gradually progressing into a mature state. Common applications of supercapacitors are in electric vehicles, hybrid electric vehicles, uninterruptible power supply (UPS) and in portable devices such as cellular phones and laptops. The capacitance values range from fractional Farads to few thousand Farads and their continuos DC voltage ratings are from 2V to 6V. At University of Waikato, a team works on using supercapacitors for improving the efficiency of linear voltage regulators. In particular, this patented technique aims at combining off the shelfs LDO ICs and a supercapacitor array for improving end to end efficiency of linear regulator. My work is aimed at developing the theoretical background and designing prototype circuitry for a voltage regulator for the case of unregulated input supply is more than 3 times of the minimum input voltage requirement of the LDO which is applicable for a 5V to 1.5V regulator. Experimental results are indicated with future suggestions for improvement

Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

Development of high-performance low-dropout regulators for SoC applications.

Or, Pui Ying."July 2010."Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.Includes bibliographical references.Abstracts in English and Chinese.AcknowledgmentsTable of ContentList of FiguresList of TablesList of PublicationsChapter Chapter 1 - --- Background of LDO ResearchChapter 1.1 --- Structure of a LDO --- p.1-1Chapter 1.2 --- Principle of Operation of LDO --- p.1-2Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4Chapter 1.6 --- An Advanced LDO Structure --- p.1-4Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5References --- p.1-6Chapter Chapter 2 - --- PSRR AnalysisChapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6Chapter 2.3 --- Conclusion of Chapter --- p.2-12References --- p.2-13Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike DetectionChapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7Chapter 3.3 --- Experimental Results --- p.3-15Chapter 3.4 --- Conclusion of Chapter --- p.3-21References --- p.3-22Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting TechniqueChapter 4.1 --- Proposed LDO --- p.4-3Chapter 4.2 --- Experimental Results --- p.4-7Chapter 4.3 --- Comparison --- p.4-11Chapter 4.4 --- Conclusion of Chapter --- p.4-12Reference --- p.4-13Chapter Chapter 5 - --- Conclusion and Future Wor

A Silicon Carbide Linear Voltage Regulator for High Temperature Applications

Current market demands have pushed the capabilities of silicon to the edge. High temperature and high power applications require a semiconductor device to operate reliably in very harsh environments. This situation has awakened interests in other types of semiconductors, usually with a higher bandgap than silicon\u27s, as the next venue for the fabrication of integrated circuits (IC) and power devices. Silicon Carbide (SiC) has so far proven to be one of the best options in the power devices field. This dissertation presents the first attempt to fabricate a SiC linear voltage regulator. This circuit would provide a power management option for developing SiC processes due to its relatively simple implementation and yet, a performance acceptable to today\u27s systems applications. This document details the challenges faced and methods needed to design and fabricate the circuit as well as measured data corroborating design simulation results

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

A Ringamp-Assisted, Output Capacitor-less Analog CMOS Low-Dropout Voltage Regulator

Continued advancements in state-of-the-art integrated circuits have furthered trends toward higher computational performance and increased functionality within smaller circuit area footprints, all while improving power efficiencies to meet the demands of mobile and battery-powered applications. A significant portion of these advancements have been enabled by continued scaling of CMOS technology into smaller process node sizes, facilitating faster digital systems and power optimized computation. However, this scaling has degraded classic analog amplifying circuit structures with reduced voltage headroom and lower device output resistance; and thus, lower available intrinsic gain. This work investigates these trends and their impact for fine-grain Low-Dropout (LDO) Voltage Regulators, leading to a presented design methodology and implementation of a state-of-the-art Ringamp-Assisted, Output Capacitor-less Analog CMOS LDO Voltage Regulator capable of both power scaling and process node scaling for general SoC applications

Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier

This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load. During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small

Wireless Power Transfer

Wireless power transfer techniques have been gaining researchers' and industry attention due to the increasing number of battery-powered devices, such as mobile computers, mobile phones, smart devices, intelligent sensors, mainly as a way to replace the standard cable charging, but also for powering battery-less equipment. The storage capacity of batteries is an extremely important element of how a device can be used. If we talk about battery-powered electronic equipment, the autonomy is one factor that may be essential in choosing a device or another, making the solution of remote powering very attractive. A distinction has to be made between the two forms of wireless power transmission, as seen in terms of how the transmitted energy is used at the receiving point: - Transmission of information or data, when it is essential for an amount of energy to reach the receiver to restore the transmitted information; - Transmission of electric energy in the form of electromagnetic field, when the energy transfer efficiency is essential, the power being used to energize the receiving equipment. The second form of energy transfer is the subject of this book