An asynchronous soft-output Viterbi algorithm decoder.

Chan Wing-kin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 69-72).Abstracts in English and Chinese.Abstract of this thesis entitled: --- p.ii摘要 --- p.ivAcknowledgements --- p.vTable of Contents --- p.viList of Figures --- p.viiiList of Tables --- p.xChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Communication Systems --- p.1Chapter 1.2 --- Soft-output Viterbi Decoder and Turbo Code --- p.2Chapter 1.3 --- Iterative Decoding --- p.3Chapter 1.4 --- Motivation --- p.3Chapter 1.5 --- Organization of the Thesis --- p.4Chapter Chapter 2 --- Self-timed Circuit Design Methodology --- p.5Chapter 2.1 --- Properties of Self-Timed Design --- p.5Chapter 2.2 --- Bundled-data Protocol --- p.7Chapter 2.3 --- Two-phase verses Four-phase Handshaking --- p.8Chapter 2.4 --- Completion-Detection and Delay Match --- p.9Chapter 2.5 --- Muller Pipeline --- p.11Chapter 2.6 --- Design of the Adder --- p.12Chapter 2.6.1 --- Basic Structure --- p.12Chapter 2.6.2 --- Carry Chain and Completion Detection --- p.12Chapter Chapter 3 --- SOVA Theory --- p.15Chapter 3.1 --- Convolutional Encoder --- p.15Chapter 3.2 --- Hard verse Soft Decision Decoding --- p.17Chapter 3.3 --- Soft Output Viterbi Algorithm --- p.17Chapter 3.3.1 --- Viterbi Algorithm --- p.17Chapter 3.3.2 --- Soft Output Algorithm --- p.20Chapter Chapter 4 --- Proposed SOVA Decoder Design --- p.24Chapter 4.1 --- Overview --- p.24Chapter 4.2 --- SOVA Decoder Architecture --- p.24Chapter 4.3 --- Branch Metric Unit --- p.26Chapter 4.3.1 --- Branch Metric Generation --- p.26Chapter 4.3.2 --- Implementation --- p.27Chapter 4.4 --- Add-Compare-Select Unit --- p.28Chapter 4.4.1 --- Basics --- p.28Chapter 4.4.2 --- Self-timed design --- p.28Chapter 4.4.3 --- Metric Normalization --- p.30Chapter 4.4.4 --- ACS Unit Implementation --- p.31Chapter 4.5 --- Traceback Unit --- p.33Chapter 4.5.1 --- Viterbi Algorithm Traceback --- p.33Chapter 4.5.2 --- Two Step SOVA --- p.34Chapter 4.5.3 --- Past Designs --- p.36Chapter 4.5.4 --- New Traceback Architecture --- p.38Chapter 4.5.5 --- Traceback operation --- p.40Chapter 4.5.6 --- Traceback Implementation --- p.42Chapter 4.5.7 --- Control Signals --- p.48Chapter Chapter 5 --- Experimental Result and Discussion --- p.54Chapter 5.1 --- Chip Fabrication --- p.54Chapter 5.2 --- Measurements --- p.61Chapter Chapter 6 --- Conclusion --- p.67References --- p.69Appendix --- p.73Pin Assignment of the SOVA test chip --- p.7

The design of an asynchronous BCJR/MAP convolutional channel decoder.

The digital design alternative to the everyday synchronous circuit design paradigm is the asynchronous model. Asynchronous circuits are also known as handshaking circuits and they may prove to be a feasible design alternative in the modern digital Very Large Scale Integration (VLSI) design environment. Asynchronous circuits and systems offer the possibility of lower system power requirements, reduced noise, elimination of clock skew and many other benefits. Channel coding is a useful means of eliminating erroneous transmission due to the communication channel\u27s physical limits. Convolutional coding has come to the forefront of channel coding discussions due to the usefulness of turbo codes. The niche market for turbo codes have typically been in satellite communication. The usefulness of turbo codes are now expanding into the next generation of handheld communication products. It is probable that the turbo coding scheme will reside in the next cellular phone one purchases [1]. Turbo coding uses two BCJR decoders in its implementation. The BCJR decoding algorithm was named after its creators Bahl, Cocke, Jelinek, and Raviv (BCJR). The BCJR algorithm is sometimes known as a Maximum Priori Posteriori (MAP) algorithm. This means a very large part of the turbo coding research will encompass the BCJR/MAP decoder and its optimization for size, power and performance. An investigation into the design of a BCJR/MAP convolutional channel decoder will be introduced. This will encompass the use and synthesis of an asynchronous Hardware Definition Language (HDL) called Balsa. The design will be carried through to the gate implementation level. Proper gate level analysis will identify the key metrics that will determine the feasibility of an asynchronous design of that of the everyday clocked paradigm.* *This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation).Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .P47. Source: Masters Abstracts International, Volume: 43-05, page: 1782. Adviser: Kemal Tepe. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

The development of an error-correcting scheme for use with a six-tone HF modem

This thesis describes the development of an error correcting system for a H.F. modem employing 6-tone Multi-Frequency Shift Keying (MFSK) as its modulation scheme. The modulation scheme was chosen to be compatible with equipment already in service and to eliminate the need to modify the existing communications infrastructure. A convolutional code together with either Viterbi decoding or Fano decoding is chosen to provide the error correction because of the potential power of such codes and because it is possible for these combinations of code and decoding method to work with any alphabet size. To detect whether correction has been successful a Cyclic Redundancy Check (CRC) is embedded within the data block before encoding.A method of using a convolutional code to provide variable rate is presented. The method uses a systematic code so that it is possible for the scheme to have a quick look to see if the first data transmission has been received error free. A search for good codes is undertaken and the effect the alphabet size has on the code spectra discussed. It is shown that a good generator sequence for a binary code is also a good generator sequence for non-binary codes.To decode the convolutional code both the Viterbi maximum likelihood decoder and the Fano sequential decoder are studied. It is argued that the Fano sequential decoder is the better choice for this application because it makes better use of system resources which will be limited in the field equipment. It is also shown that the performance of multi-level codes is better than binary codes and that an alphabet size of around 6 is optimum.The throughput of the variable rate scheme and a number of fixed rate schemes is examined. It is shown that the variable rate scheme provides the best throughput at all data rates and that the throughput improvement at the higher data rates is greatest. The effect of interleaving is also examined and results presented.To support the variable rate scheme a protocol is developed that can be used on practical H.F. channels. The potential problems with errors on both the forward and return channel are analysed and mechanisms to deal with these built-in

Circuit design for logic automata

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 143-148).The Logic Automata model is a universal distributed computing structure which pushes parallelism to the bit-level extreme. This new model drastically differs from conventional computer architectures in that it exposes, rather than hides, the physics underlying the computation by accommodating data processing and storage in a local and distributed manner. Based on Logic Automata, highly scalable computing structures for digital and analog processing have been developed; and they are verified at the transistor level in this thesis. The Asynchronous Logic Automata (ALA) model is derived by adding the temporal locality, i.e., the asynchrony in data exchanges, in addition to the spacial locality of the Logic Automata model. As a demonstration of this incrementally extensible, clockless structure, we designed an ALA cell library in 90 nm CMOS technology and established a "pick-and-place" design flow for fast ALA circuit layout. The work flow gracefully aligns the description of computer programs and circuit realizations, providing a simpler and more scalable solution for Application Specific Integrated Circuit (ASIC) designs, which are currently limited by global constraints such as the clock and long interconnects. The potential of the ALA circuit design flow is tested with example applications for mathematical operations. The same Logic Automata model can also be augmented by relaxing the digital states into analog ones for interesting analog computations. The Analog Logic Automata (AnLA) model is a merge of the Analog Logic principle and the Logic Automata architecture, in which efficient processing is embedded onto a scalable construction.(cont.) In order to study the unique property of this mixed-signal computing structure, we designed and fabricated an AnLA test chip in AMI 0.5[mu]m CMOS technology. Chip tests of an AnLA Noise-Locked Loop (NLL) circuit as well as application tests of AnLA image processing and Error-Correcting Code (ECC) decoding, show large potential of the AnLA structure.by Kailiang Chen.S.M

NASA Space Engineering Research Center for VLSI System Design

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems

CHANNEL CODING TECHNIQUES FOR A MULTIPLE TRACK DIGITAL MAGNETIC RECORDING SYSTEM

In magnetic recording greater area) bit packing densities are achieved through increasing track density by reducing space between and width of the recording tracks, and/or reducing the wavelength of the recorded information. This leads to the requirement of higher precision tape transport mechanisms and dedicated coding circuitry. A TMS320 10 digital signal processor is applied to a standard low-cost, low precision, multiple-track, compact cassette tape recording system. Advanced signal processing and coding techniques are employed to maximise recording density and to compensate for the mechanical deficiencies of this system. Parallel software encoding/decoding algorithms have been developed for several Run-Length Limited modulation codes. The results for a peak detection system show that Bi-Phase L code can be reliably employed up to a data rate of 5kbits/second/track. Development of a second system employing a TMS32025 and sampling detection permitted the utilisation of adaptive equalisation to slim the readback pulse. Application of conventional read equalisation techniques, that oppose inter-symbol interference, resulted in a 30% increase in performance. Further investigation shows that greater linear recording densities can be achieved by employing Partial Response signalling and Maximum Likelihood Detection. Partial response signalling schemes use controlled inter-symbol interference to increase recording density at the expense of a multi-level read back waveform which results in an increased noise penalty. Maximum Likelihood Sequence detection employs soft decisions on the readback waveform to recover this loss. The associated modulation coding techniques required for optimised operation of such a system are discussed. Two-dimensional run-length-limited (d, ky) modulation codes provide a further means of increasing storage capacity in multi-track recording systems. For example the code rate of a single track run length-limited code with constraints (1, 3), such as Miller code, can be increased by over 25% when using a 4-track two-dimensional code with the same d constraint and with the k constraint satisfied across a number of parallel channels. The k constraint along an individual track, kx, can be increased without loss of clock synchronisation since the clocking information derived by frequent signal transitions can be sub-divided across a number of, y, parallel tracks in terms of a ky constraint. This permits more code words to be generated for a given (d, k) constraint in two dimensions than is possible in one dimension. This coding technique is furthered by development of a reverse enumeration scheme based on the trellis description of the (d, ky) constraints. The application of a two-dimensional code to a high linear density system employing extended class IV partial response signalling and maximum likelihood detection is proposed. Finally, additional coding constraints to improve spectral response and error performance are discussed.Hewlett Packard, Computer Peripherals Division (Bristol

Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)

Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression

TDRSS multimode transponder program S-band modification

The S-Band TDRS multimode transponder and its associated ground support equipment is described. The transponder demonstrates candidate modulation techniques to provide the required information for the design of an eventual S-band transponder suitable for installation in a user satellite, capable of operating as part of a Tracking and Data Relay Satellite (TDRS) system