Ultra-low power radio transceiver for wireless sensor networks

The objective of this thesis is to present the design and implementation of ultra-low power radio transceivers at microwave frequencies, which are applicable to wireless sensor network (WSN) and, in particular, to the requirement of the Speckled Computing Consortium (or SpeckNet). This was achieved through quasi-MMIC prototypes and monolithic microwave integrated circuit (MMIC) with dc power consumption of less than 1mW and radio communication ranges operating at least one metre. A wireless sensor network is made up of widely distributed autonomous devices incorporating sensors to cooperatively monitor physical environments. There are different kinds of sensor network applications in which sensors perform a wide range of activities. Among these, a certain set of applications require that sensor nodes collect information about the physical environment. Each sensor node operates autonomously without a central node of control. However, there are many implementation challenges associated with sensor nodes. These nodes must consume extremely low power and must communicate with their neighbours at bit-rates in the order of hundreds of kilobits per second and potentially need to operate at high volumetric densities. Since the power constraint is the most challenging requirement, the radio transceiver must consume ultra-low power in order to prolong the limited battery capacity of a node. The radio transceiver must also be compact, less than 5×5 mm2, to achieve a target size for sensor node and operate over a range of at least one metre to allow communication between widely deployed nodes. Different transceiver topologies are discussed to choose the radio transceiver architecture with specifications that are required in this project. The conventional heterodyne and homodyne topologies are discussed to be unsuitable methods to achieve low power transceiver due to power hungry circuits and their high complexity. The super-regenerative transceiver is also discussed to be unsuitable method because it has a drawback of inherent frequency instability and its characteristics strongly depend on the performance of the super-regenerative oscillator. Instead, a more efficient method of modulation and demodulation such as on-off keying (OOK) is presented. Furthermore, design considerations are shown which can be used to achieve relatively large output voltages for small input powers using an OOK modulation system. This is important because transceiver does not require the use of additional circuits to increase gain or sensitivity and consequently it achieves lower power consumption in a sensor node. This thesis details the circuit design with both a commercial and in-house device technology with ultra-low dc power consumption while retaining adequate RF performance. It details the design of radio building blocks including amplifiers, oscillators, switches and detectors. Furthermore, the circuit integration is presented to achieve a compact transceiver and different circuit topologies to minimize dc power consumption are described. To achieve the sensitivity requirements of receiver, a detector design method with large output voltage is presented. The receiver is measured to have output voltages of 1mVp-p for input powers of -60dBm over a 1 metre operating range while consuming as much as 420μW. The first prototype combines all required blocks using an in-house GaAs MMIC process with commercial pseudomorphic high electron mobility transistor (PHEMT). The OOK radio transceiver successfully operates at the centre frequency of 10GHz for compact antenna and with ultra-low power consumption and shows an output power of -10.4dBm for the transmitter, an output voltage of 1mVp-p at an operating range of 1 metre for the receiver and a total power consumption of 840μW. Based on this prototype, an MMIC radio transceiver at the 24GHz band is also designed to further improve the performance and reduce the physical size with an advanced 50nm gate-length GaAs metamorphic high electron mobility transistor (MHEMT) device technology

Design and Analysis of Binary Driven Coherent M-ary Qam Transmitter for Next Generation Optical Networks

This work presents a design for a binary driven optical square M-ary quadrature amplitude modulation (QAM) transmitter for high speed optical networks. The transmitter applies tandem quadrature phase shift keying (QPSK) modulators to eliminate the need for linear broadband amplifiers and high-resolution digital to analog converters (DACs), which are both required by conventional transmitters. The transmitter design could be scaled to any order of square M-ary QAM by simply adding more QPSK modulators in tandem. It also provides a Gray coded symbol constellation, insuring the lowest bit error rate possible during symbol recovery. We also provide the design for the coupling ratios of the optical couplers that take into account the insertion loss of the optical components, in order to generate a proper 16-QAM and 64-QAM symbol constellation with equally-spaced symbols. Additionally, we analyze the impact of coupling ratio errors as well as phase errors on the bit error rate (BER) performance and constellation diagrams. The performance is tested using the OptiSystem simulation at 50 Gbaud and under presence of additive white Gaussian noise (AWGN), which demonstrated high quality symbol constellation and a BER performance similar to theoretical expectations. For 16-QAM, a BER better than 10-4 and power penalty of about 2 dB are achieved for coupling ratio errors less than 10 %, or phase errors within ±7 degrees. The 64-QAM transmitter, on the other hand, demonstrated a BER better than 10-4 and power penalty of about 1 dB for coupling ratio errors less than 4%, or phase errors within ±2 degrees. Adviser: Lim Nguye

A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance

Radio receivers should be robust to large out-of-band blockers with small degradation in their sensitivity. N-path mixers can be used as mixer-first receivers [1] with good linearity and RF filtering [2]. However, 1/f noise calls for large active device sizes for IF circuits and high power consumption. The 1/f noise issue can be relaxed by having RF gain. However, to avoid desensitization by large out-of-band blockers, a bandpass filter (BPF) with sharp cut-off frequency is required in front of the RF amplifiers. gm-C BPFs suffer from tight tradeoffs among DR, power consumption, Q and fc. Also, on-chip Q-enhanced LC BPFs [3] are not suitable due to low DR, large area and non-tunability. Therefore, bulky and non-tunable SAW filters are used. N-path BPFs offer high Q while their center frequency is tuned by the clock frequency [2]. Compared to gm-C filters, this technique decouples the required Q from the DR. The 4-path filter in [4] has only 2nd-order filtering and limited rejection. The order and rejection of N-path BPFs can be increased by cascading [5], but this renders a “round” passband shape. The 4th-order 4-path BPF in [6] has a “flat” passband shape and high rejection but a high NF. This work solves the noise issue of [6] while achieving the same out-of-band linearity and adding 25dB of voltage gain to relax the noise requirement of the subsequent stages

Proposal for Slepian-States-Based DV- and CV-QKD Schemes Suitable for Implementation in Integrated Photonics Platforms

Quantum key distribution (QKD) leverages underlying principles of quantum mechanics to realize distribution of keys with verifiable security. Despite appealing features of QKD, there are some fundamental and technical challenges that need to be solved prior to its widespread applications. First, QKD secret-key rate (SKR) is fundamentally limited by channel loss, as dictated by the rate-loss tradeoff. Quantum repeaters would be an ultimate solution to overcome this problem; however, they are well beyond the reach. The second challenge lies in the scalability and cost. Future's QKD systems must be suitable for mass production with low cost, reliable realignment-free operations, and small power consumption. To solve for these problems in a simultaneous manner, we propose to encode information in the orthogonal Slepian sequences' bases. Such an approach is highly robust against turbulence effects in free-space optical links and dispersion effects/fiber non-linearities in fiber-optics channels, thereby improving QKD distance. Moreover, exploiting multidimensional encoding space enables high spectral efficiency QKD so that the SKR can be significantly improved. Critically, generation, processing, and detection of Slepian states can be reliably implemented in an integrated quantum photonics platform, based on both reflective and transmissive waveguide Bragg gratings (WBGs). Proposed reflective/transmissive WBG-based Slepian states are applicable to both discrete variable and continuous variable QKD systems.Multidisciplinary University Research Initiatives Office of Naval Research [N00014-13-1-0627]; National Science FoundationOpen access journalThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at [email protected]

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Silicon Germanium BiCMOS Integrated Circuits for Scalable Cryogenic Sensing Applications

This dissertation is focused on an investigation of BiCMOS cryogenic low noise amplifiers (LNAs) based on Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for simultaneous low noise and low power design and also taking advantage of CMOS circuitry for adding flexibility to the LNA design. Cryogenic LNAs\u27 scalability challenges are discussed and addressed in the dissertation. To achieve that, first, HBTs of three state-of-the-art technologies are characterized and modeled at cryogenic temperature. It is shown that SiGe HBT provides a promising compromise of noise temperature, power consumption, and bandwidth. Moreover, a scalable on-chip approach is proposed and verified for biasing of SiGe HBTs based LNAs. Finally, the first cryogenic re-configurable LNA is designed, implemented, and measured

A Fully Integrated CMOS Receiver.

The rapidly growing wireless communication market is creating an increasing demand for low-cost highly-integrated radio frequency (RF) communication systems. This dissertation focuses on techniques to enable fully-integrated, wireless receivers incorporating all passive components, including the antenna, and also incorporating baseband synchronization on-chip. Not only is the receiver small in size and requires very low power, but it also delivers synchronized demodulated data. This research targets applications such as implantable neuroprosthetic devices and environmental wireless sensors, which need short range, low data-rate wireless communications but a long lifetime. To achieve these goals, the super-regenerative architecture is used, since power consumption with this architecture is low due to the simplified receiver architecture. This dissertation presents a 5GHz single chip receiver incorporating a compact on-chip 5 GHz slot antenna (50 times smaller than traditional dipole antennas) and a digital received data synchronization. A compact capacitively-loaded 5 GHz standing-wave resonator is used to improve the energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. A new type of low-power envelope detector is incorporated to increase the data rate and efficiency. The receiver achieves a data rate up to 1.2 Mb/s, dissipates 6.6 mW from a 1.5 V supply. The novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed instead of a conventional low-Q on-chip inductor. The simulated quality factor of the resonator is very high (35), and is verified by phase-noise measurements of a prototype 5GHz Voltage Control Oscillator (VCO) incorporating this resonator. The prototype VCO, implemented in 0.13 µm CMOS, dissipates 3 mW from a 1.2 V supply, and achieves a measured phase noise of -117 dBc/Hz at a 1 MHz offset. In the on-chip antenna an efficient shielding technique is used to shield the antenna from the low-resistivity substrate underneath. Two standalone on-chip slot antenna prototypes were designed and fabricated in 0.13 µm CMOS. The 9 GHz prototype occupies a die area of only 0.3 mm2, has an active gain of -4.4 dBi and an efficiency of 9%. The second prototype occupies a die area of 0.47 mm2, and achieves a passive gain of approximately -17.0 dBi at 5 GHz.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60739/1/shid_1.pd

Spaceborne sensors (1983-2000 AD): A forecast of technology

A technical review and forecast of space technology as it applies to spaceborne sensors for future NASA missions is presented. A format for categorization of sensor systems covering the entire electromagnetic spectrum, including particles and fields is developed. Major generic sensor systems are related to their subsystems, components, and to basic research and development. General supporting technologies such as cryogenics, optical design, and data processing electronics are addressed where appropriate. The dependence of many classes of instruments on common components, basic R&D and support technologies is also illustrated. A forecast of important system designs and instrument and component performance parameters is provided for the 1983-2000 AD time frame. Some insight into the scientific and applications capabilities and goals of the sensor systems is also given

Design Of Tunable Single Band And Concurrent Low Noise Amplifier

Penguat hingar rendah (LNA) merupakan kunci utama binaan blok rantaian penerimaan kerana ia bertujuan untuk menguatkan isyarat sambil menambah hingar seminima yang mungkin. Sehubungan itu, beberapa jenis teknik bagi meminimumkan hingar LNA diperkenalkan. PCSNIM (kuasa terhad dengan hingar dan input sepadan serempak) dilihat antara teknik yang banyak diberikan perhatian. Namun, berdasarkan kepada kajian sebelum ini, ia menghadkan keupayaan gandaan LNA. Bagi menyelesaikan permasalahan ini dan menyokong keperluan pelbagai jalur, tesis ini mempersembahkan empat jenis rekaan LNA (LNA1 hingga LNA4) berdasarkan sumber induktif merosot (ISD) untuk meliputi jalur tunggal (contoh: IEEE802.11.b/g, Bluetooth) dan serempak (contoh: WIFI). LNA1 disasar untuk menyelesaikan isu gandaan yang rendah bagi jalur tunggal LNA dengan penambahbaikan pada keluarannya. Bagi mendapatkan penerimaan serempak untuk dua jalur frekuensi (24.5/5.2 GHz piawaian WIFI), LNA3 direka berasaskan topologi yang sama untuk LNA1. LNA ini dilaksanakan dalam struktur penuh-bersepadu untuk menyahkan penggunaan komponen luaran cip. Rekaan LNA2 dan LNA4 terhasil daripada masalah anjakan frekuensi selepas proses fabrikasi LNA1 dan LNA3. Bagi menangani isu ini, struktur boleh tala menggunakan varaktor digunakan pada padanan masukan/keluaran LNA2 dan sistem baru GPAPU (unit analog boleh program kegunaan umum) diperkenal dan dilaksana kepada struktur penguat boleh tala-serempak (LNA4). Kesemua kaedah dibuktikan secara simulasi dan pengukuran. LNA1, LNA2 dan LNA3 difabrikasi menggunakan teknologi 0.13 μm CMOS manakala LNA4 direka hanya pada tahap pra susun atur simulasi. Untuk LNA1, pengukuran gandaan hadapan dan hingar memberikan nilai 19.84 dB dan 2.59 dB. Bagi masukan/keluaran sepadan, nilai diperolehi adalah -9.39 dB dan -39.23 dB. LNA1 menggunakan arus terus 4 mA daripada bekalan kuasa 1.2 V. Sementara itu, terdapat anjakan frekuensi sebanyak 260 MHz pada keluaran LNA1. Ini disebabkan proses toleransi semasa fabrikasi. Nilai pengukuran bagi gandaan hadapan dan hingar bagi LNA2 adalah 14.62 dB dan 3.73 dB dengan kuasa arus terus 5 mW. Untuk julat talaan, 140 MHz pada masukan dan 50 MHz pada keluaran berjaya dicapai untuk padanan masukan/keluaran. Berdasarkan kepada struktur talaan varaktor pada masukan dan keluaran LNA2, nilai dapatan (terutamanya NF) berubah-ubah bergantung kepada padanan masukan/keluaran. Ini bertujuan untuk mencapai fungsi boleh tala jika dibandingkan dengan LNA1. Nilai pengukuran yang diperoleh bagi gandaan hadapan LNA3 ialah 17.11 dB pada 2.45 GHz dan 10.42 dB pada 5.2 GHz dengan kuasa arus terus 4.8 mW. Nilai pengukuran bagi padanan masukan dan keluaran pula adalah -19.48 dB dan -39.23 dB bagi jalur rendah manakala -25.51 dB dan -10.46 dB bagi jalur tinggi. Nilai hingar yang diukur untuk LNA3 ialah 4.09 dB pada jalur rendah dan 10.47 dB untuk jalur tinggi. Nilai yang diperoleh bagi bacaan gandaan dan nilai hingar berbeza daripada jangkaan awal. Ini kerana, terlihatkan anjakan frekuensi sebanyak 1 GHz pada jalur atas yang dipengaruhi oleh proses perubahan semasa fabrikasi. Daripada hasil simulasi, LNA4 menunjukkan gandaan hadapan yang dicapai bagi jalur rendah ialah 21 dB dan jalur tinggi 18 dB. Untuk nilai hingar, 2.53 dB diperolehi bagi jalur rendah dan 2.96 dB bagi jalur tinggi dengan kuasa arus terus 5.5 mW. Bagi rangkaian keluaran untuk LNA4, julat nilai boleh tala yang diperolehi ialah 300 MHz. Kesimpulannya, kaedah penambahbaikan gandaan yang digunakan bagi LNA1 berfungsi dengan jayanya dan isu nilai gandaan yang rendah berasaskan teknik PCSNIM dapat diselesaikan. Begitu juga masalah anjakan frekuensi dalam penguat jalur tunggal diatasi menggunakan struktur boleh tala LNA2. Tambahan pula, penguat PCSNIM serempak penuh-bersepadu (LNA3) yang direka dan dilaksanakan berjaya menerima frekuensi-frekuensi bagi piawaian WIFI secara serempak. Akhir sekali, struktur boleh tala yang baru (GPAPU) diperkenalkan dan terbukti berfungsi berdasarkan kepada keputusan simulasi LNA4. ________________________________________________________________________________________________________________________ Low noise amplifier (LNA) is one of the key building blocks in receiving chain as they aimed to amplify the signal while adding minimum possible noise to it. Thus, several noise optimization techniques were proposed by researchers to minimize the noise of LNAs. Among these techniques, the PCSNIM (power constrained simultaneous noise and input matching) is found to be a popular approach; however, it limits the gain of the LNA according to literature. Therefore, to tackle the mentioned issue and to support the requirement for multi-band, this thesis presents the design of four LNAs (LNA1 to LNA4) based on inductive source degenerated (ISD) to cover single-band (e.g. IEEE 802.11.b/g, Bluetooth) and concurrent (e.g. WIFI) applications. LNA1 is targeted to solve the reduced-gain issue of single-band LNA by utilizing a gain-enhancer at the output of LNA. To obtain the concurrent reception of two frequency bands (2.45/ 5.2 GHz in WIFI standard), LNA3 is designed based on the same topology of LNA1. This LNA is implemented in fully-integrated structure to eliminate the off-chip components. Meanwhile, the design of LNA2 and LNA4 are resulted from the problem of frequency shift that occurred after the fabrication of LNA1 and LNA3. Hence, to tackle the issue, a tunable structure using varactors is used at the input/output matching of LNA2 and a new system (GPAPU-general purpose analog programmable unit) is introduced and implemented to the concurrent structure to obtain the tunable-concurrent amplifier (LNA4). For this work, LNA1, LNA2, and LNA3 were fabricated in 0.13 μm CMOS technology while LNA4 was designed only up to pre-layout simulation level. The measured forward gain and noise figure (NF) values for LNA1 are 19.84 dB and 2.59 dB respectively, while achieving the input/output return losses of -9.39 dB and -39.23 dB. LNA1 consumes 4 mA of dc current from 1.2 V supply. Meanwhile, 260 MHz frequency-shift was observed at the output of LNA1 due to the process tolerances during fabrication. The measured forward gain and NF values of LNA2 are 14.62 dB and 3.73 dB respectively, while consuming 5 mW of dc power. Moreover, the tuning ranges of 140 MHz at the input and 50 MHz at output are accomplished by LNA2 for the input/output matching. Due to the varactor-based tuning structure at the input and output of LNA2, the gain (and respectively NF) was traded-off with input/output matching to achieve tunable function comparing to LNA1. LNA3 is measured with the forward gain values of 17.11 and 10.42 dB at 2.45 and 5.2 GHz frequencies respectively, while consuming 4.8 mW of dc power. Also, the obtained values for input and output return losses are -19.48 and -39.23 dB respectively at the lower band and -25.51 and -10.64 dB respectively at upper band. The measured NF of this LNA3 is 4.09 dB at the lower-band and 10.47 dB at the upper band. The achieved gain and NF are different from the expected simulation results due to the observed 1 GHz frequency-shift at upper-band due to process variation during fabrication. From the simulation results of LNA4, the forward gain values obtained for lower and upper bands are 21 and 18 dB respectively. Also, the achieved NF values are 2.53 and 2.96 dB respectively in the mentioned bands while consuming 5.5 mW of dc power. In addition, the output network of the LNA4 can be tuned in range of 300 MHz. In conclusion, the implemented method of gain-enhancer in LNA1 works perfectly and the reduced-gain issue of PCSNIM technique is solved. Also, the problem of frequency-shift in single-band amplifier was tackled using the tunable structure of LNA2. Furthermore, a fully-integrated concurrent PCSNIM amplifier (LNA3) is designed and implemented successfully to receive simultaneous frequency bands of WIFI standard. Finally, a new tunable structure (GPAPU) was introduced and theoretically proved to be functional based on the simulation results of LNA4