Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors

This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N0001414135

Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications

Advanced correlation filters have been employed in a wide variety of image processing and pattern recognition applications such as automatic target recognition and biometric recognition. Among those, object recognition and tracking have received more attention recently due to their wide range of applications such as autonomous cars, automated surveillance, human-computer interaction, and vehicle navigation.Although digital signal processing has long been used to realize such computational systems, they consume extensive silicon area and power. In fact, computational tasks that require low to moderate signal-to-noise ratios are more efficiently realized in analog than digital. However, analog signal processing has its own caveats. Mainly, noise and offset accumulation which degrades the accuracy, and lack of a scalable and standard input/output interface capable of managing a large number of analog data.Two digitally-interfaced analog correlation filter systems are proposed. While digital interfacing provided a standard and scalable way of communication with pre- and post-processing blocks without undermining the energy efficiency of the system, the multiply-accumulate operations were performed in analog. Moreover, non-volatile floating-gate memories are utilized as storage for coefficients. The proposed systems incorporate techniques to reduce the effects of analog circuit imperfections.The first system implements a 24x57 Gilbert-multiplier-based correlation filter. The I/O interface is implemented with low-power D/A and A/D converters and a correlated double sampling technique is implemented to reduce offset and lowfrequency noise at the output of analog array. The prototype chip occupies an area of 3.23mm2 and demonstrates a 25.2pJ/MAC energy-efficiency at 11.3 kVec/s and 3.2% RMSE.The second system realizes a 24x41 PWM-based correlation filter. Benefiting from a time-domain approach to multiplication, this system eliminates the need for explicit D/A and A/D converters. Careful utilization of clock and available hardware resources in the digital I/O interface, along with application of power management techniques has significantly reduced the circuit complexity and energy consumption of the system. Additionally, programmable transconductance amplifiers are incorporated at the output of the analog array for offset and gain error calibration. The prototype system occupies an area of 0.98mm2 and is expected to achieve an outstanding energy-efficiency of 3.6pJ/MAC at 319kVec/s with 0.28% RMSE

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl

Study of Single-Event Transient Effects on Analog Circuits

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment. Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects. The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance

Time-Domain/Digital Frequency Synchronized Hysteresis Based Fully Integrated Voltage Regulator

abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required. The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking. The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Temperature sensors in SOI CMOS for high temperature applications

Ph.DDOCTOR OF PHILOSOPH

Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltage VDD down to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (around VDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201