Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

SiGe BiCMOS ICs for X-Band 7-Bit T/R module with high precision amplitude and phase control

Over the last few decades, phased array radar systems had been utilizing Transmit/Receive (T/R) modules implemented in III-V semiconductor based technologies. However, their high cost, size, weight and low integration capability created a demand for seeking alternative solutions to realize T/R modules. In recent years, SiGe BiCMOS technologies are rapidly growing their popularity in T/R module applications by virtue of meeting high performance requirements with more reduced cost and power dissipation with respect to III-V technologies. The next generation phased array radar systems require a great number of fully integrated, high yield, small-scale and high accuracy T/R modules. In line with these trends, this thesis presents the design and implementation of the first and only 7-Bit X-Band T/R module with high precision amplitude and phase control in the open literature, which is realized in IHP 0.25μ SiGe BiCMOS technology. In the scope of this thesis, sub-blocks of the designed T/R module such as low noise amplifier (LNA), inter-stage amplifier, SiGe Hetero-Junction Bipolar Transistor (HBT) Single- Pole Double-Throw (SPDT) switch and 7-Bit digitally controlled step attenuator are extensively discussed. The designed LNA exhibits Noise Figure (NF) of 1.7 dB, gain of 23 dB, Output Referred Compression Point (OP1dB) of 16 dBm while the inter-stage amplifier gives measured NF of 3 dB, gain of 15 dB and OP1dB of 18 dBm. Moreover, the designed SPDT switch has an Insertion Loss (IL) of 1.7 dB, isolation of 40 dB and OP1dB of 28 dBm. Lastly, the designed 7-Bit SiGe HBT digitally controlled step attenuator demonstrates IL of 8 dB, RMS attenuation error of 0.18 dB, RMS phase error of 2° and OP1dB of 16 dBm. The 7-Bit T/R module is constructed by using the sub-blocks given above, along with a 7- Bit phase shifter (PS) and a power amplifier (PA). Post-layout simulation results show that the designed T/R module exhibits a gain of 38 dB, RMS phase error of 2.6°, RMS amplitude error of 0.82 dB and Rx-Tx isolation of 80 dB across X-Band. The layout of T/R module occupies an area of 11.37 mm2

SiGe BiCMOS front-end circuits for X-Band phased arrays

The current Transmit/Receive (T/R) modules have typically been implemented using GaAs- and InP-based discrete monolithic microwave integrated circuits (MMIC) to meet the high performance requirement of the present X-Band phased arrays. However their cost, size, weight, power consumption and complexity restrict phased array technology only to certain military and satellite applications which can tolerate these limitations. Therefore, next generation X-Band phased array radar systems aim to use low cost, silicon-based fully integrated T/R modules. For this purpose, this thesis explores the design of T/R module front-end building blocks based on new approaches and techniques which can pave the way for implementation of fully integrated X-Band phased arrays in low-cost SiGe BiCMOS process. The design of a series-shunt CMOS T/R switch with the highest IP1dB, compared to other reported works in the literature is presented. The design focuses on the techniques, primarily, to achieve higher power handling capability (IP1dB), along with higher isolation and better insertion loss of the T/R switch. Also, a new T/R switch was implemented using shunt NMOS transistors and slow-wave quarter wavelength transmission lines. It presents the utilization of slow-wave transmissions lines in T/R switches for the first time in any BiCMOS technology to the date. A fully integrated DC to 20 GHz SPDT switch based on series-shunt topology was demonstrated. The resistive body oating and on-chip impedance transformation networks (ITN) were used to improve power handling of the switch. An X-Band high performance low noise ampli er (LNA) was implemented in 0.25 μm SiGe BiCMOS process. The LNA consists of inductively degenerated two cascode stages with high speed SiGe HBT devices to achieve low noise gure (NF), high gain and good matching at the input and output, simultaneously. The performance parameters of the LNA collectively constitute the best Figure-of-Merit value reported in similar technologies, to the best of author's knowledge. Furthermore, a switched LNA was implemented SiGe BiCMOS process for the first time at X-Band. The resistive body floating technique was incorporated in switched LNA design, for the first time, to improve the linearity of the circuit further in bypass mode. Finally, a complete T/R module with a state-of-the-art performance was implemented using the individually designed blocks. The simulations results of the T/R module is presented in the dissertation. The state-of-the-art performances of the presented building blocks and the complete module are attributed to the unique design methodologies and techniques

An X-Band power amplifier design for on-chip RADAR applications

Tremendous growth of RAdio Detecting And Ranging (RADAR) and communication electronics require low manufacturing cost, excellent performance, minimum area and highly integrated solutions for transmitter/receiver (T/R) modules, which are one of the most important blocks of RADAR systems. New circuit topologies and process technologies are investigated to fulfill these requirements of next generation RADAR systems. With the recent improvements, Silicon-Germanium Bipolar CMOS technology became a good candidate for recently used III-V technologies, such as GaAs, InP, and GaN, to meet high speed and performance requirements of present RADAR applications. As new process technologies are used, new solutions and circuit architectures have to be provided while taking into account the advantages and disadvantageous of used technologies. In this thesis, a new T/R module system architecture is presented for single/onchip X-Band phased array RADAR applications. On-chip T/R module consists of five blocks; T/R switch, single-pole double-throw (SPDT) switch, low noise amplifier (LNA), power amplifier (PA), and phase shifter. As the main focus of this thesis, a two-stage power amplifier is realized, discussed and measured. Designed in IHP's 0.25 [micrometer] SiGe BiCMOS process technology, the power amplifier operates in Class-A mode to achieve high linearity and presents a measured small-signal gain of 25 dB at 10 GHz. While achieving an output power of 22 dBm, the power amplifier has drain efficiency of 30 % in saturation. The total die area is 1 [square millimeters], including RF and DC pads. To our knowledge, these results are comparable to and/or better than those reported in the literature

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

Phased-Array Antenna-in-Package Technology for Emerging Millimeter Wave Applications

The ever-increasing data rates for wireless technologies (e.g., satellite communications, fifth generation (5G) wireless communications, and automotive radars) has directed the interests towards millimeter wave (mm-Wave) technology that provides wider absolute bandwidth. Relatively small size of antennas at mm-Wave makes large-scale phased-array antenna (PAA) system a feasible solution to compensate for the path loss and alleviate the requirements of the RF transceiver front-ends at mm-Wave. Despite developments in the military applications for more than 50 years, active PAA systems have been costly for commercial applications. The high cost is mainly due to the discrete implementation of transmit/receive beamforming modules where III-V front-end monolithic microwave integrated circuits (MMICs) (GaAs or InP, or both) are assembled together with silicon-based chips used for address decoders, power management, and general digital control such as phase and gain setting and calibration. A paradigm shift happened when silicon-based phased arrays had been implemented starting with the work at Caltech using silicon-germanium (SiGe) bipolar CMOS (BiCMOS) and Si CMOS technologies. Silicon-based technologies (Si-CMOS and SiGe-BiCMOS) are not costly and are able to be produced in a large scale. On the other side, multilayer antenna-in-package (AiP) technology is currently the prevailing antenna and packaging technology for miscellaneous mm-Wave applications. These two technologies together make low-cost, low-power active PAA possible. A modular and scalable silicon-based phased-array AiP could be the building block for the development of large-scale mm-Wave PAA systems where hundreds to thousands of antenna elements are required in order to provide a reliable communication link. This approach not only ease the complexity of the system, but also makes the implementation of the system over any conformal geometry feasible. In this thesis, two different architectures for phased-array AiP are presented. The first architecture is a 4×4 active transmit phased-array AiP with polarization control at Ka-band. The second architecture is a 4×4 bi-directional antenna array with integrated passive beamformer with left-handed circular polarization (LHCP) radiation. In chapter II, a 4×4 active transmit phased-array AiP with polarization control at Ka-band is discussed. Silicon-based active transmit phased-array AiP is able to realize any kind of polarization including linear and circular polarization besides providing relatively high effective isotropic radiated power (EIRP). The proposed active AiP is modular and scalable and is able to be employed as the unit cell for a large-scale phased-array antenna system. It consists of 16 dual- linearly polarized cavity-backed patch antennas, four 8-channel active beamformers, and a four-way splitter network. The proposed AiP provides 42 dB of active gain at the boresight. The (EIRP) of the current module is 41 dBm at the 1-dB compression point of the active beamformer chips and it consumes 2.6 W of DC power when the system radiates left-handed circular polarization at the boresight. Calibration and radiation pattern measurement of the system is also discussed and the measurement results for a case of left-handed circularly polarized (LHCP) radiation is presented. In chapter III, a 4×4 bi-directional antenna array with integrated passive beamformer with left-handed circular polarization (LHCP) radiation is presented. Hybrid approach that combines active and passive PAA architectures is an alternative solution in lowering the cost and complexity of active PAA systems. The design and implementation aspects of a 4×4 antenna array with integrated passive beamformer for low-cost and efficient millimeter wave applications is presented. The phase shifter’s operational principle and actuation mechanism are discussed in detail. Slow-wave structure is employed to shrink the size of the phase shifter. The simulation and measurement results of the phase shifter are presented. Measurement results show the maximum insertion loss of 2.2 dB in all the tuning states and the insertion loss variation is 1.2 dB. Also, it provides 380º of the phase tuning range in a compact footprint area of 2.4 mm × 3 mm. 2D P-PAA is designed, simulated and measured over the operating band. Measurement results show the antenna‘s main beam can be steered over an angular range of ±30º in both elevation and azimuth planes.. The operating frequency bandwidth of the system ranges from 28-30 GHz. The antenna’s main characteristics, such as radiation pattern, directivity, efficiency, and reflection coefficient are measured and presented

Bidirectional common-path for 8-to-24 gHz low noise SiGe BiCMOS T/R module core-chip

This thesis is based on the design of an 8-to-24 GHz low noise SiGe BiCMOS Transmitter/Receiver (T/R) Module core-chip in a small area by bidirectional common-path. The next-generation phased array systems require multi-functionality and multi-band operation to form multi-purpose integrated circuits. Wide bandwidth becomes a requirement for the system in various applications, such as electronic warfare, due to leading cheaper and lighter system solutions. Although III-V technologies can satisfy the high-frequency specifications, they are expensive and have a large area. The silicon-based technologies promise high integration capability with low cost, but they sacrifice from the performance to result in desired bandwidth. The presented dissertation targets system and circuit level solutions on the described content. The wideband core-chip utilized a bidirectional common path to surpass the bandwidth limitations. The bidirectionality enhances the bandwidth, noise, gain and area of the transceiver by the removal of the repetitive blocks in the unidirectional common chain. This approach allows succeeding desired bandwidth and compactness without sacrificing from the other high-frequency parameters. The realized core-chip has 31.5 and 32 dB midband gain for the receiver and transmitter respectively, with a + 2.1 dB /GHz of positive slope. Its RMS phase and amplitude errors are lower than 5.60 and 0.8 dB, respectively for 4-bit of resolution. The receiver noise figure is lower than 5 dB for the defined bandwidth while dissipating 112 mW of power in a 5.5 mm2 area. The presented results verify the advantage of the favored architecture and might replace the III-V based counterparts

SiGe Millimeter-Wave (W-Band) Down-Converter for Phased Focal Plane Array

A millimeter-wave (W-Band) down-converter for Phased Focal Plane Arrays (PFPAs) has been designed and fabricated using the IBM Silicon-Germanium (SiGe) BiCMOS 8HP process technology. The radio frequency (RF) input range of the down-converter chip is from 70 95GHz. The intermediate frequency (IF) range is from 5 30GHz. The local oscillator (LO) frequency is fixed at 65GHz. The down-converter chip has been designed to achieve a conversion gain greater than 20dB, a noise figure (NF) below 10dB and input return loss greater than 10dB. The chip also has novel LO circuitry facilitating LO feed-through among down-converters chips in parallel. This wide bandwidth down-converter will be part of millimeter-wave PFPA receiver designed and fabricated in collaboration with the University of Massachusetts-Amherst Department of Astronomy. This PFPA receiver will be installed on Green Bank Telescope (GMT) / Large millimeter wave telescope (LMT) in Q2 of 2014. This project is collaboration between the University of Massachusetts-Amherst (UMass), Brigham Young University (BYU) and National Radio Astronomy Observatory (NRAO). To the best of the author’s knowledge, this is first wide bandwidth down-converter at W-band to achieve this high gain and low noise figure among Si/SiGe based systems

Design of Fully-Integrated High-Resolution Radars in CMOS and BiCMOS Technologies

The RADAR, acronym that stands for RAdio Detection And ranging, is a device that uses electromagnetic waves to detect the presence and the distance of an illuminated target. The idea of such a system was presented in the early 1900s to determine the presence of ships. Later on, with the approach of World War II, the radar gained the interest of the army who decided to use it for defense purposes, in order to detect the presence, the distance and the speed of ships, planes and even tanks. Nowadays, the use of similar systems is extended outside the military area. Common applications span from weather surveillance to Earth composition mapping and from flight control to vehicle speed monitoring. Moreover, the introduction of new ultrawideband (UWB) technologies makes it possible to perform radar imaging which can be successfully used in the automotive or medical field. The existence of a plenty of known applications is the reason behind the choice of the topic of this thesis, which is the design of fully-integrated high-resolution radars. The first part of this work gives a brief introduction on high resolution radars and describes its working principle in a mathematical way. Then it gives a comparison between the existing radar types and motivates the choice of an integrated solution instead of a discrete one. The second part concerns the analysis and design of two CMOS high-resolution radar prototypes tailored for the early detection of the breast cancer. This part begins with an explanation of the motivations behind this project. Then it gives a thorough system analysis which indicates the best radar architecture in presence of impairments and dictates all the electrical system specifications. Afterwards, it describes in depth each block of the transceivers with particular emphasis on the local oscillator (LO) generation system which is the most critical block of the designs. Finally, the last section of this part presents the measurement results. In particular, it shows that the designed radar operates over 3 octaves from 2 to 16GHz, has a conversion gain of 36dB, a flicker-noise-corner of 30Hz and a dynamic range of 107dB. These characteristics turn into a resolution of 3mm inside the body, more than enough to detect even the smallest tumor. The third and last part of this thesis focuses on the analysis and design of some important building blocks for phased-array radars, including phase shifter (PHS), true time delay (TTD) and power combiner. This part begins with an exhaustive introduction on phased array systems followed by a detailed description of each proposed lumped-element block. The main features of each block is the very low insertion loss, the wideband characteristic and the low area consumption. Finally, the major effects of circuit parasitics are described followed by simulation and measurement results