7,056 research outputs found
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
This paper presents a unified, comprehensive approach
to the design of continuous-time (CT) and discrete-time
(DT) cellular neural networks (CNN) using CMOS current-mode
analog techniques. The net input signals are currents instead
of voltages as presented in previous approaches, thus avoiding
the need for current-to-voltage dedicated interfaces in image
processing tasks with photosensor devices. Outputs may be either
currents or voltages. Cell design relies on exploitation of current
mirror properties for the efficient implementation of both linear
and nonlinear analog operators. These cells are simpler and
easier to design than those found in previously reported CT
and DT-CNN devices. Basic design issues are covered, together
with discussions on the influence of nonidealities and advanced
circuit design issues as well as design for manufacturability
considerations associated with statistical analysis. Three prototypes
have been designed for l.6-pm n-well CMOS technologies.
One is discrete-time and can be reconfigured via local logic for
noise removal, feature extraction (borders and edges), shadow
detection, hole filling, and connected component detection (CCD)
on a rectangular grid with unity neighborhood radius. The other
two prototypes are continuous-time and fixed template: one for
CCD and other for noise removal. Experimental results are given
illustrating performance of these prototypes
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature extraction, noise filtering , compound component detection, etc.) using the cellular neural network paradigm. Area evaluation for the new model shows a reduction off about 50% as compared to the use of current-mode techniques with conventional models. Experimental measurements of CMOS prototypes designed in a 1.6 μm n-well double-metal single-poly technology are reported
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