A Switch Architecture for Real-Time Multimedia Communications

In this paper we present a switch that can be used to transfer multimedia type of trafJic. The switch provides a guaranteed throughput and a bounded latency. We focus on the design of a prototype Switching Element using the new technology opportunities being offered today. The architecture meets the multimedia requirements but still has a low complexity and needs a minimum amount of hardware. A main item of this paper will be the background of the architectural design decisions made. These include the interconnection topology, buffer organization, routing and scheduling. The implementation of the switching fabric with FPGAs, allows us to experiment with switching mode, routing strategy and scheduling policy in a multimedia environment. The witching elements are interconnected in a Kautz topology. Kautz graphs have interesting properties such as: a small diametec the degree is independent of the network size, the network is fault-tolerant and has a simple routing algorithm

Photonic Combinatorial Network for Contention Management in 160 Gb/s Interconnection Networks based on All-Optical 2x2 Switching Elements

A modular photonic interconnection network based on a combination of basic 2×2 all-optical nodes including a photonic combinatorial network for the packet contention management is presented. The proposed architecture is synchronous, can handle optical time division multiplexed (OTDM) packets up to 160 Gb/s, exhibits self-routing capability, and very low switching latency. In such a scenario, OTDM has to be preferred to wavelength division multiplexing (WDM) because in the former case, the instantaneous packet power carries the information related to only one bit, making the signal processing based on instantaneous nonlinear interactions between packets and control signals more efficient. Moreover, OTDM can be used in interconnection networks without caring about the propagation impairments because of the very short length (< 100 m) of the links in these networks. For such short-range networks, the packet synchronization can be solved at the network boundary in the electronic domain without the need of complex optical synchronizers. In this paper, we focus on a photonic combinatorial network able to detect the contentions, and to optically drive the contention resolution block and the switching control block. The implementation of the photonic combinatorial network is based on semiconductor devices, which makes the solution very promising in terms of compactness, stability, and power consumption. This implementation represents the first example of complex photonic combinatorial network for ultrafast digital processing. The network performance has been investigated for bit streams at 10 Gb/s in terms of bit error rate (BER) and contrast ratio. Moreover, the suitability of the 2×2 photonic node architecture exploiting the earlier mentioned combinatorial network has been verified at a bit rate up to 160 Gb/s. In this way, the potential of photonic digital processing for the next generation broad band and flexible interconnection networks has been demonstrated

High capacity photonic integrated switching circuits

As the demand for high-capacity data transfer keeps increasing in high performance computing and in a broader range of system area networking environments; reconfiguring the strained networks at ever faster speeds with larger volumes of traffic has become a huge challenge. Formidable bottlenecks appear at the physical layer of these switched interconnects due to its energy consumption and footprint. The energy consumption of the highly sophisticated but increasingly unwieldy electronic switching systems is growing rapidly with line rate, and their designs are already being constrained by heat and power management issues. The routing of multi-Terabit/second data using optical techniques has been targeted by leading international industrial and academic research labs. So far the work has relied largely on discrete components which are bulky and incurconsiderable networking complexity. The integration of the most promising architectures is required in a way which fully leverages the advantages of photonic technologies. Photonic integration technologies offer the promise of low power consumption and reduced footprint. In particular, photonic integrated semiconductor optical amplifier (SOA) gate-based circuits have received much attention as a potential solution. SOA gates exhibit multi-terahertz bandwidths and can be switched from a high-gain state to a high-loss state within a nanosecond using low-voltage electronics. In addition, in contrast to the electronic switching systems, their energy consumption does not rise with line rate. This dissertation will discuss, through the use of different kind of materials and integration technologies, that photonic integrated SOA-based optoelectronic switches can be scalable in either connectivity or data capacity and are poised to become a key technology for very high-speed applications. In Chapter 2, the optical switching background with the drawbacks of optical switches using electronic cores is discussed. The current optical technologies for switching are reviewed with special attention given to the SOA-based switches. Chapter 3 discusses the first demonstrations using quantum dot (QD) material to develop scalable and compact switching matrices operating in the 1.55µm telecommunication window. In Chapter 4, the capacity limitations of scalable quantum well (QW) SOA-based multistage switches is assessed through experimental studies for the first time. In Chapter 5 theoretical analysis on the dependence of data integrity as ultrahigh line-rate and number of monolithically integrated SOA-stages increases is discussed. Chapter 6 presents some designs for the next generation of large scale photonic integrated interconnects. A 16x16 switch architecture is described from its blocking properties to the new miniaturized elements proposed. Finally, Chapter 7 presents several recommendations for future work, along with some concluding remark

Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

4 pagesInternational audienceFor high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques

Dynamic Systolization for Developing Multiprocessor Supercomputers

A dynamic network approach is introduced for developing reconfigurable, systolic arrays or wavefront processors; This allows one to design very powerful and flexible processors to be used in a general-purpose, reconfigurable, and fault-tolerant, multiprocessor computer system. The concepts of macro-dataflow and multitasking can be integrated to handle variable-resolution granularities in computationally intensive algorithms. A multiprocessor architecture, Remps, is proposed based on these design methodologies. The Remps architecture is generalized from the Cedar, HEP, Cray X- MP, Trac, NYU ultracomputer, S-l, Pumps, Chip, and SAM projects. Our goal is to provide a multiprocessor research model for developing design methodologies, multiprocessing and multitasking supports, dynamic systolic/wavefront array processors, interconnection networks, reconfiguration techniques, and performance analysis tools. These system design and operational techniques should be useful to those who are developing or evaluating multiprocessor supercomputers

INTRODUCING AN OPTIMAL QCA CROSSBAR SWITCH FOR BASELINE NETWORK

Crossbar switch is the basic component in multi-stage interconnection networks. Therefore, this study was conducted to investigate performance of a crossbar switch with two multiplexers. The presented crossbar switch was simulated using quantum-dot cellular automata (QCA) technology and QCA Designer software, and was studied and optimized in terms of cell number, occupied area, number of clocks, and energy consumption. Using the provided crossbar switch, the baseline network was designed to be optimal in terms of cell number and occupied area. Also, the number of input states was investigated and simulated to verify accuracy of the baseline network. The proposed crossbar switch uses 62 QCA cells and the occupied area by the switch is equal to 0.06µm2 and its latency equals 4 clock zones, which is more efficient than the other designs. In this paper, using the presented crossbar switch, the baseline network was designed with 1713 cells, and occupied area of 2.89µm2

Microring-Resonator-Based Switch Architectures for Optical Networks

Integrated silicon photonics provides a promising platform for chip-based, high-speed optical signal processing due to its compatibility with complementary metal-oxide semiconductor (CMOS) fabrication processes. They are attracting significant research and development interest globally and making a huge impact on green information and communication technologies, and high-performance computing systems. Microring resonators (MRRs) show the versatility to implement a variety of network functions, compact footprint, and complementary metal-oxide semiconductor compatibility, and demonstrate the viability applied in photonic integrated technologies for both chip level and board-to-board interconnects. Furthermore, MRRs have excellent wavelength selection properties and can be used to design tunable filters, modulators, wavelength converters, and switches that are critical components for optical interconnects. The research work of this dissertation is focused on investigating how to develop MRR-based switches and switch architectures for possible applications not only in optical interconnection networks but also in flexible-grid on-chip networks for optical communication systems. The basic properties and performances of the MRR switches and the MRR switch architectures related to their applications in the networks are examined. In particular, how to design and how to configure high performance, bandwidth variable, low insertion loss, and weak crosstalk MRR-based switches and switch architectures are investigated for applications in optical interconnection networks and in flexible-grid on-chip networks for optical communication systems. The works include several parts as follows. The physical characteristics of microring resonator switching devices are thoroughly analyzed using a model based on the field coupling matrix theory. The spectral response and insertion loss properties of these switching elements are simulated using the developed model. Then we investigate the optimal design of high-order MRR-based switch devices. Spectral shaping of the passbands of microring resonator switches is studied. Multistage high-order microring resonator-based optical switch structures are proposed to achieve steep-edge flat-top spectral passband. Using the transfer matrix analysis model, the spectral response behaviors of the switch structures are simulated. The performances of the proposed multistage high-order microring resonator-based optical switch structures and the high-order microring-resonator-based optical switch structures without stages are studied and compared. Two types of MRR-based switch architectures are proposed to realize variable output bandwidths varying from 0 to 4 THz. One consists of 320, 160, and 80 third-order MRR switches with -3 dB passband widths of 12.5, 25, and 50 GHz, respectively. Another one is two-stage switch structure. In the first stage there are 4 third-order MRR switches with the passband widths of 1 THz. In second stage, there are 80, 40, 20 third-order MRR switches with the passband widths of 12.5, 25, and 50 GHz, respectively. Their insertion losses and crosstalks in the worst cases are numerically analyzed and compared in order to show the feasibility for the architectures to be applied in flexible optical networks. MRR-based bandwidth-variable wavelength selective switch architectures with multiple input and output ports are proposed for flexible optical networks. The light transmission behaviors of a 1 by N MRR-based WSS are analyzed in detail based on numerical simulation using transfer matrix theory. Two types of N by N MRR-based WSS architectures consisting of MRR-based WSSs and MRR-based WSSs, and MRR-based WSSs and optical couplers are proposed. The performances of the proposed architectures are studied. Scalable optical interconnections based on MRRs are proposed, which consist mainly of microring resonator devices: microring lasers, microring switches, microring de-multiplexers, and integrated photo-dectors. Their throughput capacities, end-to-end time latencies, and transmission packet loss rates are evaluated using OMNet++. In summary, the research of the dissertation contributes to develop high performance, variable bandwidth, low insertion loss, and low crosstalk MRR-based optical switches and switch architectures to adapt to dynamic source allocation of flexible-grid optical networks