Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM

This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively

The Miniaturization of the AFIT Random Noise Radar

Advances in technology and signal processing techniques have opened the door to using an UWB random noise waveform for radar imaging. This unique, low probability of intercept waveform has piqued the interest of the U.S. DoD as well as law enforcement and intelligence agencies alike. While AFIT\u27s noise radar has made significant progress, the current architecture needs to be redesigned to meet the space constraints and power limitations of an aerial platform. This research effort is AFIT\u27s first attempt at RNR miniaturization and centers on two primary objectives: 1) identifying a signal processor that is compact, energy efficient, and capable of performing the demanding signal processing routines and 2) developing a high-speed correlation algorithm that is suited for the target hardware. A correlation routine was chosen as the design goal because of its importance to the noise radar\u27s ability to estimate the presence of a return signal. Furthermore, it is a computationally intensive process that was used to determine the feasibility of the processing component. To determine the performance of the proposed algorithm, results from simulation and experiments involving representative hardware were compared to the current system. Post-implementation reports of the FPGA-based correlator indicated zero timing failures, less than a Watt of power consumption, and a 44% utilization of the Virtex-5\u27s logic resources

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

New FFT/IFFT Factorizations with Regular Interconnection Pattern Stage-to-Stage Subblocks

Les factoritzacions de la FFT (Fast Fourier Transform) que presenten un patró d’interconnexió regular entre factors o etapes son conegudes com algorismes paral·lels, o algorismes de Pease, ja que foren originalment proposats per Pease. En aquesta contribució s’han desenvolupat noves factoritzacions amb blocs que presenten el patró d’interconnexió regular de Pease. S’ha mostrat com aquests blocs poden ser obtinguts a una escala prèviament seleccionada. Les noves factoritzacions per ambdues FFT i IFFT (Inverse FFT) tenen dues classes de factors: uns pocs factors del tipus Cooley-Tukey i els nous factors que proporcionen la mateix patró d’interconnexió de Pease en blocs. Per a una factorització donada, els blocs comparteixen dimensions, el patró d’interconnexió etapa a etapa i a més cada un d’ells pot ser calculat independentment dels altres.FFT (Fast Fourier Transform) factorizations presenting a regular interconnection pattern between factors or stages are known as parallel algorithms, or Pease algorithms since were first proposed by Pease. In this paper, new FFT/IFFT (Inverse FFT) factorizations with blocks that exhibit regular Pease interconnection pattern are derived. It is shown these blocks can be obtained at a previously selected scale. The new factorizations for both the FFT and IFFT have two kinds of factors: a few Cooley-Tukey type factors and new factors providing the same Pease interconnection pattern property in blocks. For a given factorization, these blocks share dimensions, the interconnection pattern stage-to-stage, and all of them can be calculated independently from one another.Las factoritzaciones de la FFT (Fast Fourier Transform) que presentan un patrón de interconexiones regular entre factores o etapas son conocidas como algoritmos paralelos, o algoritmos de Pease, puesto que fueron originalmente propuestos por Pease. En esta contribución se han desarrollado nuevas factoritzaciones en subbloques que presentan el patrón de interconexión regular de Pease. Se ha mostrado como estos bloques pueden ser obtenidos a una escalera previamente seleccionada. Las nuevas factoritzaciones para ambas FFT y IFFT (Inverse FFT) tienen dos clases de factores: unos pocos factores del tipo Cooley-Tukey y los nuevos factores que proporcionan el mismo patrón de interconexión de Pease en bloques. Para una factoritzación dada, los bloques comparten dimensiones, patrón d’interconexión etapa a etapa y además cada uno de ellos puede ser calculado independientemente de los otros

An FPGA-based 77 GHzs RADAR signal processing system for automotive collision avoidance

An FPGA implementable Verilog HDL based signal processing algorithm has been developed to detect the range and velocity of target vehicles using a MEMS based 77 GHz LFMCW long range automotive radar. The algorithm generates a tuning voltage to control a GaAs based VCO to produce a triangular chirp signal, controls the operation of MEMS components, and finally processes the IF signal to determine the range and veolicty of the detected targets. The Verilog HDL code has been developed targeting the Xilinx Virtex-5 SX50T FPGA. The developed algorithm enables the MEMS radar to detect 24 targets in an optimum timespan of 6.42 ms in the range of 0.4 to 200 m with a range resolution of 0.19 m and a maximum range error 0.25 m. A maximum relative velocity of ±300 km/h can be determined with a velocity resolution in HDL of 0.95 m/s and a maximum velocity error of 0.83 m/s with a sweep duration of 1 ms

Signal Subspace Processing in the Beam Space of a True Time Delay Beamformer Bank

A number of techniques for Radio Frequency (RF) source location for wide bandwidth signals have been described that utilize coherent signal subspace processing, but often suffer from limitations such as the requirement for preliminary source location estimation, the need to apply the technique iteratively, computational expense or others. This dissertation examines a method that performs subspace processing of the data from a bank of true time delay beamformers. The spatial diversity of the beamformer bank alleviates the need for a preliminary estimate while simultaneously reducing the dimensionality of subsequent signal subspace processing resulting in computational efficiency. The pointing direction of the true time delay beams is independent of frequency, which results in a mapping from element space to beam space that is wide bandwidth in nature. This dissertation reviews previous methods, introduces the present method, presents simulation results that demonstrate the assertions, discusses an analysis of performance in relation to the Cramer-Rao Lower Bound (CRLB) with various levels of noise in the system, and discusses computational efficiency. One limitation of the method is that in practice it may be appropriate for systems that can tolerate a limited field of view. The application of Electronic Intelligence is one such application. This application is discussed as one that is appropriate for a method exhibiting high resolution of very wide bandwidth closely spaced sources and often does not require a wide field of view. In relation to system applications, this dissertation also discusses practical employment of the novel method in terms of antenna elements, arrays, platforms, engagement geometries, and other parameters. The true time delay beam space method is shown through modeling and simulation to be capable of resolving closely spaced very wideband sources over a relevant field of view in a single algorithmic pass, requiring no course preliminary estimation, and exhibiting low computational expense superior to many previous wideband coherent integration techniques

Signal Subspace Processing in the Beam Space of a True Time Delay Beamformer Bank

A number of techniques for Radio Frequency (RF) source location for wide bandwidth signals have been described that utilize coherent signal subspace processing, but often suffer from limitations such as the requirement for preliminary source location estimation, the need to apply the technique iteratively, computational expense or others. This dissertation examines a method that performs subspace processing of the data from a bank of true time delay beamformers. The spatial diversity of the beamformer bank alleviates the need for a preliminary estimate while simultaneously reducing the dimensionality of subsequent signal subspace processing resulting in computational efficiency. The pointing direction of the true time delay beams is independent of frequency, which results in a mapping from element space to beam space that is wide bandwidth in nature. This dissertation reviews previous methods, introduces the present method, presents simulation results that demonstrate the assertions, discusses an analysis of performance in relation to the Cramer-Rao Lower Bound (CRLB) with various levels of noise in the system, and discusses computational efficiency. One limitation of the method is that in practice it may be appropriate for systems that can tolerate a limited field of view. The application of Electronic Intelligence is one such application. This application is discussed as one that is appropriate for a method exhibiting high resolution of very wide bandwidth closely spaced sources and often does not require a wide field of view. In relation to system applications, this dissertation also discusses practical employment of the novel method in terms of antenna elements, arrays, platforms, engagement geometries, and other parameters. The true time delay beam space method is shown through modeling and simulation to be capable of resolving closely spaced very wideband sources over a relevant field of view in a single algorithmic pass, requiring no course preliminary estimation, and exhibiting low computational expense superior to many previous wideband coherent integration techniques

Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System

The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO) imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16 virtual elements synthesized from the MIMO antenna array. The chirp signal generater is based on a combination of direct digital synthesizer (DDS) and phase locked loop (PLL). A signal conditioning circuit is used to deal with the coupling effect within the array. The signal processing platform is based on an efficient field programmable gates array (FPGA) and digital signal processor (DSP) pipeline where a robust beamforming imaging algorithm is running on. The radar system was evaluated through a real field experiment. Imaging capability and real-time performance shown in the results demonstrate the practical feasibility of the implementation