A low-complexity self-calibrating adaptive quadrature receiver

In this paper digital part of a self-calibrating quadrature-receiver is described, containing a digital calibration-engine. The blind source-separation-based calibration-engine eliminates the RF-impairments in real-time hence improving the receiver's performance without the need for test/pilot tones, trimming or use of power-hungry discrete components. Furthermore, an efficient time-multiplexed calibration-engine architecture is proposed and implemented on an FPGA utilising a reduced-range multiplier structure. The use of reduced-range multipliers results in substantial reduction of area as well as power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier. The performance of the calibration-engine does not depend on the modulation format or the constellation size of the received signal; hence it can be easily integrated into the digital signal processing paths of any receiver

Adaptive self-calibrating image rejection receiver

An adaptive self-calibrating image rejection receiver is described, containing a modified Weaver image rejection mixer and a Digital Image Rejection Processor (DIRP). The blind source-separation-based DIRP eliminates the I/Q errors improving the Image Rejection Ratio (IRR) without the need for trimming or use of power-hungry discrete components. Hardware complexity is minimal, requiring only two complex coefficients; hence it can be easily integrated into the signal processing path of any receiver. Simulation results show that the proposed approach achieves 75-97 dB of IRR

Design and low-power implementation of an adaptive image rejection receiver

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures

Living and dealing with RF impairments in communication transceivers

This paper provides an overview of the sources and effects of the RF impairments limiting and rendering the performance of the future wireless communication transceivers costly as well as hindering their wide-spread use in commercial products. As transmission bandwidths and carrier frequencies increase effect of these impairments worsen. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments in terms of bit-error-rate and image rejection ratio. The paper also give highlights of the various aspects of the research carried out in mitigating the effects of these impairments primarily in the digital signal processing domain at the baseband as well as providing low-complexity hardware implementations of such algorithms incorporating a number of power and area saving techniques

Low complexity blind and data-aided IQ imbalance compensation methods for low-IF receivers

Low-IF and Zero-IF (direct conversion) down converters showed a great potential in implementing multi standard single chip solutions, eliminating the need to use off chip components and so reduce the area and the cost of the wireless receivers. One of the main performance limitations in the low-IF & Zero-IF down-converters is the components mismatch between the in-phase path and the quadrature-path named the IQ Imbalance (IQI) which limits the achievable image rejection ratio (IRR) of the down converters. Many techniques had been proposed to enhance the achievable IRR either by using calibration methods, e.g. using lab calibration, or by doing online compensation during signal reception. In this work those techniques are reviewed, proposing three new methods for blind IQI compensation techniques, the first proposed method targets the low input signal to interference ratio (low SIRin) while the second and third methods targets the moderate and high SIRin, showing that the proposed methods reach better performance and/or lower complexity than the methods already introduced in the literature. Also two techniques to perform data aided IQI compensation are introduced exploiting pilot symbols within the desired signal with no prior knowledge about the image signal. The first method exploits a preamble sequence assuming slow fading condition while the second approach exploits a sequence of pilots to compensate for the IQI being suitable for fast fading conditions as well. Simulation results showed that the proposed data aided techniques achieved shorter convergence time and higher image rejection ratio compared to the blind methods at high SNR values

A low complexity DSP driven analog impairment mitigation scheme for low-IF GNSS receivers

Due to the increasing demands for location based services within the wireless mass-market; there has been relentless pressure to reduce both the chip area and power dissipation of the user terminal. Low-IF receivers combine the advantages of superheterodyne and direct-conversion architectures offering a highly integrated solution while avoiding the issues associated with DC offsets and flicker noise. The main drawback of the low-IF architecture is its limited image rejection due to analog impairments. In this paper, the sources of the impairments are analyzed for a low-IF receiver operating at the GPS/Galileo L1 band together with a novel low-complexity solution to compensate for them in the DSP domain is proposed. For processing the combined GPS/Galileo L1 signal, a signal simulator we call GNSScope has been developed together with a low-IF receiver model to analyze the influence of the analog impairments. The idea behind our proposed novel adaptive compensator which estimates and compensates for the imbalances and mismatches is that in the absence of these mismatches no correlation exists between the desired and the image channels, which is not the case when impairments are present. Results show that through the deployment of the proposed approach, image-rejection performance can be enhanced by 75 dB. This enhancement in the image-rejection performance subsequently results in relaxed analog front-end specifications leading to high levels of integration making it possible for highly integrated software-defined Global Navigation Satellite Systems (GNSS) receiver to be realistically and economically designed and implemented

Impact of a photodiode's angular characteristics on RSS-based VLP accuracy

Photodiode (PD)-based Visible Light Positioning (VLP)-based localisation systems seem propitious for the low-cost tracking and route-configurable navigation of automated guided vehicles, found in warehouse settings. Delivering the required high accuracy, currently necessitates measuring and fitting the received power - distance relation. This paper shows that accurately modelling the PD receiver & x2019;s angular characteristics obsoletes this calibrating fit, while still providing accurate positioning estimates. A new responsivity model Square (SQ) is proposed, which is a function of the square of the incidence angle rather than its cosine. Both its aptitude in matching real-life propagation and its associated localisation accuracy are verified using two extensive measurement sets, each detailing the propagation of a PD moving across a 2D plane 3 m below a 4-LED plane. SQ is compared to the responsivity and calibration fit models available in the literature. In conjunction with model-based fingerprinting positioning, SQ outscores the Lambertian and generalised Lambertian model in terms of the 90(th) percentile root-mean-square error (rMSE) $p_{90}$ by 45.36 cm (83.1 & x0025;) and 0.84 cm (8.4 & x0025;) respectively for the non-Lambertian-like receiver. $SQ$ exhibits an equivalent performance as the generalised Lambertian model for the Lambertian-like photodiode. Accounting for the appropriate receiver model can also boost trilateration & x2019;s rMSE. A 50(th) percentile rMSE reduction of respectively 1.87 cm and 2.66 cm is found in the setup

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Solutions pour l'auto-adaptation des systèmes sans fil

The current demand on ubiquitous connectivity imposes stringent requirements on the fabrication of Radio-Frequency (RF) circuits. Designs are consequently transferred to the most advanced CMOS technologies that were initially introduced to improve digital performance. In addition, as technology scales down, RF circuits are more and more susceptible to a lot of variations during their lifetime, as manufacturing process variability, temperature, environmental conditions, aging… As a result, the usual worst-case circuit design is leading to sub-optimal conditions, in terms of power and/or performance most of the time for the circuit. In order to counteract these variations, increasing the performances and also reduce power consumption, adaptation strategies must be put in place.More importantly, the fabrication process introduces more and more performance variability, which can have a dramatic impact on the fabrication yield. That is why RF designs are not easily fabricated in the most advanced CMOS technologies, as 32nm or 22nm nodes for instance. In this context, the performances of RF circuits need to be calibrated after fabrication so as to take these variations into account and recover yield loss.This thesis work is presenting on a post-fabrication calibration technique for RF circuits. This technique is performed during production testing with minimum extra cost, which is critical since the cost of test can be comparable to the cost of fabrication concerning RF circuits and cannot be further raised. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit.Our proposed methodology has first been demonstrated with simulation data with an RF power amplifier as a case study. Afterwards, a silicon demonstrator has then been fabricated in a 65nm technology in order to fully demonstrate the methodology. The fabricated dataset of circuits is extracted from typical and corner wafers. This feature is very important since corner circuits are the worst design cases and therefore the most difficult to calibrate. In our case, corner circuits represent more than the two third of the overall dataset and the calibration can still be proven. In details, fabrication yield based on 3 sigma performance specifications is increased from 21% to 93%. This is a major performance of the technique, knowing that worst case circuits are very rare in industrial fabrication.La demande courante de connectivité instantanée impose un cahier des charges très strict sur la fabrication des circuits Radio-Fréquences (RF). Les circuits doivent donc être transférées vers les technologies les plus avancées, initialement introduites pour augmenter les performances des circuits purement numériques. De plus, les circuits RF sont soumis à de plus en plus de variations et cette sensibilité s’accroît avec l’avancées des technologies. Ces variations sont par exemple les variations du procédé de fabrication, la température, l’environnement, le vieillissement… Par conséquent, la méthode classique de conception de circuits “pire-cas” conduit à une utilisation non-optimale du circuit dans la vaste majorité des conditions, en termes de performances et/ou de consommation. Ces variations doivent donc être compensées, en utilisant des techniques d’adaptation.De manière plus importante encore, le procédé de fabrication des circuits introduit de plus en plus de variabilité dans les performances des circuits, ce qui a un impact important sur le rendement de fabrication des circuits. Pour cette raison, les circuits RF sont difficilement fabriqués dans les technologies CMOS les plus avancées comme les nœuds 32nm ou 22nm. Dans ce contexte, les performances des circuits RF doivent êtres calibrées après fabrication pour prendre en compte ces variations et retrouver un haut rendement de fabrication.Ce travail de these présente une méthode de calibration post-fabrication pour les circuits RF. Cette méthodologie est appliquée pendant le test de production en ajoutant un minimum de coût, ce qui est un point essentiel car le coût du test est aujourd’hui déjà comparable au coût de fabrication d’un circuit RF et ne peut être augmenté d’avantage. Par ailleurs, la puissance consommée est aussi prise en compte pour que l’impact de la calibration sur la consommation soit minimisé. La calibration est rendue possible en équipant le circuit avec des nœuds de réglages et des capteurs. L’identification de la valeur de réglage optimale du circuit est obtenue en un seul coup, en testant les performances RF une seule et unique fois. Cela est possible grâce à l’utilisation de capteurs de variations du procédé de fabrication qui sont invariants par rapport aux changements des nœuds de réglage. Un autre benefice de l’utilisation de ces capteurs de variation sont non-intrusifs et donc totalement transparents pour le circuit sous test. La technique de calibration a été démontrée sur un amplificateur de puissance RF utilisé comme cas d’étude. Une première preuve de concept est développée en utilisant des résultats de simulation.Un démonstrateur en silicium a ensuite été fabriqué en technologie 65nm pour entièrement démontrer le concept de calibration. L’ensemble des puces fabriquées a été extrait de trois types de wafer différents, avec des transistors aux performances lentes, typiques et rapides. Cette caractéristique est très importante car elle nous permet de considérer des cas de procédé de fabrication extrêmes qui sont les plus difficiles à calibrer. Dans notre cas, ces circuits représentent plus des deux tiers des puces à disposition et nous pouvons quand même prouver notre concept de calibration. Dans le détails, le rendement de fabrication passe de 21% avant calibration à plus de 93% après avoir appliqué notre méthodologie. Cela constitue une performance majeure de notre méthodologie car les circuits extrêmes sont très rares dans une fabrication industrielle