Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

A phase-locked frequency divide-by-3 optical parametric oscillator

Accurate phase-locked 3:1 division of an optical frequency was achieved, by using a continuous-wave (cw) doubly resonant optical parametric oscillator. A fractional frequency stability of 2*10^(-17) of the division process has been achieved for 100s integration time. The technique developed in this work can be generalized to the accurate phase and frequency control of any cw optical parametric oscillator.Comment: 4 pages, 5 figures in a postscript file. To appear in a special issue of IEEE Trans. Instr. & Meas., paper FRIA-2 presented at CPEM'2000 conference, Sydney, May 200

An Integrated-Photonics Optical-Frequency Synthesizer

Integrated-photonics microchips now enable a range of advanced functionalities for high-coherence applications such as data transmission, highly optimized physical sensors, and harnessing quantum states, but with cost, efficiency, and portability much beyond tabletop experiments. Through high-volume semiconductor processing built around advanced materials there exists an opportunity for integrated devices to impact applications cutting across disciplines of basic science and technology. Here we show how to synthesize the absolute frequency of a lightwave signal, using integrated photonics to implement lasers, system interconnects, and nonlinear frequency comb generation. The laser frequency output of our synthesizer is programmed by a microwave clock across 4 THz near 1550 nm with 1 Hz resolution and traceability to the SI second. This is accomplished with a heterogeneously integrated III/V-Si tunable laser, which is guided by dual dissipative-Kerr-soliton frequency combs fabricated on silicon chips. Through out-of-loop measurements of the phase-coherent, microwave-to-optical link, we verify that the fractional-frequency instability of the integrated photonics synthesizer matches the $7.0*10^{-13}$ reference-clock instability for a 1 second acquisition, and constrain any synthesis error to $7.7*10^{-15}$ while stepping the synthesizer across the telecommunication C band. Any application of an optical frequency source would be enabled by the precision optical synthesis presented here. Building on the ubiquitous capability in the microwave domain, our results demonstrate a first path to synthesis with integrated photonics, leveraging low-cost, low-power, and compact features that will be critical for its widespread use.Comment: 10 pages, 6 figure

Barrel Shifter Physical Unclonable Function Based Encryption

Physical Unclonable Functions (PUFs) are circuits designed to extract physical randomness from the underlying circuit. This randomness depends on the manufacturing process. It differs for each device enabling chip-level authentication and key generation applications. We present a protocol utilizing a PUF for secure data transmission. Parties each have a PUF used for encryption and decryption; this is facilitated by constraining the PUF to be commutative. This framework is evaluated with a primitive permutation network - a barrel shifter. Physical randomness is derived from the delay of different shift paths. Barrel shifter (BS) PUF captures the delay of different shift paths. This delay is entangled with message bits before they are sent across an insecure channel. BS-PUF is implemented using transmission gates; their characteristics ensure same-chip reproducibility, a necessary property of PUFs. Post-layout simulations of a common centroid layout 8-level barrel shifter in 0.13 {\mu}m technology assess uniqueness, stability and randomness properties. BS-PUFs pass all selected NIST statistical randomness tests. Stability similar to Ring Oscillator (RO) PUFs under environment variation is shown. Logistic regression of 100,000 plaintext-ciphertext pairs (PCPs) failed to successfully model BS- PUF behavior