6 research outputs found
HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING
In future, the radar/satellite wireless communication devices must support multiple standards
and should be designed in the form of system-on-chip (SoC) so that a significant reduction
happen on cost, area, pins, and power etc. However, in such device, the design of a fully
on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously
becomes a multifold complex problem. Further, the inherent high-power out-of-band
(OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate
the receiver. Therefore, the proper blocker rejection techniques need to be incorporated.
The primary focus of this research work is the development of a CMOS high-performance low
noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further,
the various reconfigurable mixer architectures are proposed for performance adaptability of a
wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced
fully differential receiver is proposed. The receiver composed of a composite transistor
pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor
amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based
tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture
in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver
system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides
a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB
having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured
receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm,
occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary
subthreshold receiver is proposed to estimate the out of blocker power. As a redundant
block in the system, the cost and power minimization of the auxiliary receiver are achieved
via subthreshold circuit design techniques and implementing the design in higher technology
node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the
noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power
consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver
and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various
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reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance
according to the requirement of the selected communication standard. The down conversion mixers
configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth
reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept,
the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured
result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of
-11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW
and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz
for active/passive case respectively
Blocker Tolerant Radio Architectures
Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards.
Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2.
Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS.
Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears.
Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans-
mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna
Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques
Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications.
In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies.
A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback.
For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind.
A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver
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Ultra-low power receivers for wireless sensor networks
In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed.
A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show power consumption as low as 244 μW with a sensitivity of -84 dBm while operating at 250 kbps. A second test chip designed to operate at 2.4 GHz improves on the previous design by adding full digital control and calibration. The 2.4 GHz receiver consumes 215 μW while operating at 250 kbps and shows a 12 dB improvement in sensitivity over the original design. The entire receiver has an energy consumption of only 0.175 nJ/b while operating at 2 Mbps
High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications
The prevalence of wireless standards and the introduction of dynamic
standards/applications, such as software-defined radio, necessitate the next generation
wireless devices that integrate multiple standards in a single chip-set to support a variety
of services. To reduce the cost and area of such multi-standard handheld devices,
reconfigurability is desirable, and the hardware should be shared/reused as much as
possible. This research proposes several novel circuit topologies that can meet various
specifications with minimum cost, which are suited for multi-standard applications. This
doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the
RF front-end; and 2. The analog-to-digital converter (ADC).
The first part of this dissertation focuses on LNA noise reduction and linearization
techniques where two novel LNAs are designed, taped out, and measured. The first LNA,
implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm
CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an
inductor connected at the gate of the cascode transistor and the capacitive cross-coupling
to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and
voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power
consumption. The second LNA, implemented in UMC (United Microelectronics
Corporation) 0.13Cm CMOS process, features a practical linearization technique for
high-frequency wideband applications using an active nonlinear resistor, which obtains a
robust linearity improvement over process and temperature variations. The proposed
linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB
over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior
published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized
UWB LNA achieves excellent linearity with much less power than previously published
works.
The second part of this dissertation developed a reconfigurable ADC for multistandard
receiver and video processors. Typical ADCs are power optimized for only one
operating speed, while a reconfigurable ADC can scale its power at different speeds,
enabling minimal power consumption over a broad range of sampling rates. A novel
ADC architecture is proposed for programming the sampling rate with constant biasing
current and single clock. The ADC was designed and fabricated using UMC 90nm
CMOS process and featured good power scalability and simplified system design. The
programmable speed range covers all the video formats and most of the wireless
communication standards, while achieving comparable Figure-of-Merit with customized
ADCs at each performance node. Since bias current is kept constant, the reconfigurable
ADC is more robust and reliable than the previous published works