348 research outputs found

    RF receiver design using the direct conversion approach at 5.8 GHz band based on IEEE 802.11a standard

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    This thesis presents the development and analysis of a radio frequency (RF) front-end direct conversion receiver at 5.725 – 5.825 GHz where IEEE 802.11a standard is used as performance test. The RF receiver is designed based on the commercialized products (off-the-shelf) where it focuses on the system design tradeoff, rather than circuit design tradeoff. The RF receiver has been designed with the selected architecture where it is consist of low noise amplifier (LNA), radio frequency amplifier (RFA), power divider and two bandpass filters. The modeled RF receiver has been analyzed by using Advanced Design System (ADS) 2005A software for system characteristic and performance test. From the simulation, minimum sensitivity is -91 dBm at data rate 6 Mbps and -74 dBm at data rate 54 Mbps where it is comply with the IEEE 802.11a standard. The RF receiver prototype has been measured and this system produces has gain of 39 dB which is higher than the reviewed of 37.5 dB. The noise figure of this work is measured at 1.30 dB, which is better than the reviewed work at 4.6 dB. The nonlinearity characteristic such as power at 1dB compression point (P1dB) and third order intercept point (IP3) is observed. From the measurement, the RF receiver will drop 1 dB when input power (Pin) is injected above -27 dBm then it caused output power (Pout) start saturated. The third output intercept point (OIP3) and third input intercept point (IIP3) is at around 15 dBm and -24.50 dBm respectively. The RF receiver system characteristic such as sensitivity meet the standard requirement of IEEE 802.11a standard for wireless local area network (WLAN) bridge system.

    Simulation Of Cascading LNA And RF Amplifier For Front-End Direct-Conversion Receiver At 5.8 GHz

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    In this paper, a simulation of cascaded LNA and RF amplifier for front-end direct conversion receiver at 5.8-GHz frequency band is presented. By using direct conversion architecture, the image rejection performance is improved, lower complexity and the component is reduced. The cascading LNA and RF amplifier has 27 dB gain and 2.17 dB noise figure. The LNA and RF amplifier is simulated using Ansoft Designer software and fabricated with Duroid 5880 as the microstrip material

    A Low Power 5.8GHz Fully Integrated CMOS LNA for Wireless Applications

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    A low power 5.8 GHz fully integrated CMOS low noise amplifier (LNA) with on chip spiral inductors for wireless applications is designed based on TSMC 0.18 µm technology in this paper. The cascode structure and power-constrained simultaneous noise and input matching technique are adopted to achieve low noise, low power and high gain characteristics. The proposed LNA exhibit a state of the art performance consuming only 6.4mW from a 1.8V power supply. The simulation results show that it has a noise figure (NF) only 0.972 dB, which is perfectly close to NFmin while maintaining the other performances. The proposed LNA also has an input 1-dB compression point (IP1dB) of-21.22 dBm, a power gain of 17.04 dB, and good input and output reflection coefficients, which indicate that the proposed LNA topology is very suitable for the implementation of narrowband LNAs in 802.11a wireless applications

    High frequency of low noise amplifier architecture for WiMAX application: A review

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    The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

    A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

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    The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

    Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

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    Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

    Towards a Universal Multi-Standard RF Receiver

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    Future wireless communication market calls for the need of an extreme compact wireless device that can easily access to all the available services at any time and at any location with minimum power consumption and cost. The key is to find a multi-standard wireless receiver that can cover all the service specifications while keeping redundant components to minimum. Reconfigurable concept is right fit the need. In this thesis, a fully integrated universal multi-standard receiver using low-cost CMOS technology has been proposed based on the survey for different wireless receiver specifications and optimum architectures. Tunable receiver building blocks such as filters, LNAs, Mixers, VCOs, gain blocks are the main factor to approach this novel receiver. In order to realize frequency agility, low cost as well as low power consumption, a good switch is a must. In this thesis, MEMS switches are preferred rather than active switches or active tuning elements based on their performance comparisons. In the feasibility study, as an example, first, a reconfigurable LNA and a reconfigurable oscillator using hard wires as switches have been developed, and then a LNA and an oscillator have been designed using a MEMS switch. The effect of hard-wire connection and MEMS to the circuits has been evaluated. No performance degradation has been found when using hard-wire connections, while some has been observed when using MEMS. However, MEMS could be integrated with other circuits on the same die if it could be built on low resistive silicon substrate without performance degradation

    A 5GHz1.8V low power CMOS low-noise amplifier

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    Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work
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