Power Droop Reduction In Logic BIST By Scan Chain Reordering

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

In this paper, we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in CS CMOS image sensors are recursive pseudo-random binary matrices. We have proved that the restricted isometry property of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random number generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behavior that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber reconstruction algorithm. By means of single value decomposition, we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N000141410355European Union H2020 76586

REALIZATION OF LOW TRANSITION BASED PRPG FOR POWER OPTIMIZED APPLICATIONS

This paper proposes low power pseudo random test pattern generator. This produces the necessary test patterns which are used for running the circuit under test for detecting faults. Power consumption of the circuit under test is measured by switching activity of the inside logic which depends on the randomness of applied stimulus. Power consumption is greatly increased due to the reduction of correlation between the successive vectors of applied stimulus. A modified conventional linear feedback shift register is implemented for reducing power of circuit under test by generating the patterns by reducing the utilization of hard ware. The main intension of producing intermediate patterns is to reduce the conventional activity of primary inputs (PI) that which reduces the switching activities inside the CUT and by this power consumption is reduced without using huge hardware

A Modified Test Pattern Generation Architecture for Fault Detection in BIST

Multiple test patterns varying in a single bit position is generated for built-in-self-test (BIST). The test patterns generated using Johnson Counter and Seed Vector lacks in fault coverage. So Seed vector block is eliminated and patterns varying in single bit position is generated using 8 bit Johnson Counter has been proposed to have the required fault coverage with reduced test length. The generated test patterns have an advantage of minimum transition sequence. The methodology for producing the test vectors for BIST is coded using VHDL and simulations were performed with ModelSim 10.0b. The Area utilization and the power report were manipulated with the help of Xilinx ISE 9.1 software. The area reduction of 58% and power reduction of 9% is achieved while generating test patterns using Johnson counter

A MODIFIED FAULT COVERAGE ARCHITECTURE FOR A LOW POWER BIST TEST PATTERN GENERATOR USING LP-LFSR

This paper proposes low power pseudo random Test Pattern generation .This test pattern is run on the circuit under test for desired fault coverage. The power consumed by the chip under test is a measure of the switching activity of the logic inside the chip which depends largely on the randomness of the applied input stimulus. Reduced correlation between the successive vectors of the applied stimulus into the circuit under test can result in much higher power consumption by the device than the budgeted power. A new low power pattern generation technique is implemented using a modified conventional Linear Feedback Shift Register which can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which eventually reduces the switching activities inside the Circuit under Test (CUT) and hence power consumption is also reduced without any penalty in the hardware resources

Design of Testable ripple carry adder in Quantum Dot Cellular AutomataÂ

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