Radio-Communications Architectures

Wireless communications, i.e. radio-communications, are widely used for our different daily needs. Examples are numerous and standard names like BLUETOOTH, WiFI, WiMAX, UMTS, GSM and, more recently, LTE are well-known [Baudoin et al. 2007]. General applications in the RFID or UWB contexts are the subject of many papers. This chapter presents radio-frequency (RF) communication systems architecture for mobile, wireless local area networks (WLAN) and connectivity terminals. An important aspect of today's applications is the data rate increase, especially in connectivity standards like WiFI and WiMAX, because the user demands high Quality of Service (QoS). To increase the data rate we tend to use wideband or multi-standard architecture. The concept of software radio includes a self-reconfigurable radio link and is described here on its RF aspects. The term multi-radio is preferred. This chapter focuses on the transmitter, yet some considerations about the receiver are given. An important aspect of the architecture is that a transceiver is built with respect to the radio-communications signals. We classify them in section 2 by differentiating Continuous Wave (CW) and Impulse Radio (IR) systems. Section 3 is the technical background one has to consider for actual applications. Section 4 summarizes state-of-the-art high data rate architectures and the latest research in multi-radio systems. In section 5, IR architectures for Ultra Wide Band (UWB) systems complete this overview; we will also underline the coexistence and compatibility challenges between CW and IR systems

Low-Cost Transceiver Architectures for 60 GHz Ultra Wideband WLANs

Millimeter-wave multiport transceiver architectures dedicated to 60 GHz UWB short-range communications are proposed in this paper. Multi-port circuits based on 90° hybrid couplers are intensively used for phased antenna array, millimeter-wave modulation and down-conversion, as a low-cost alternative to the conventional architecture. This allows complete integration of circuits including antennas, in planar technology, on the same substrate, improving the overall transceiver performances

60 GHz transceiver circuits in SiGe-HBT and CMOS technologies

Die Erhöhung der Übertragungsrate von Kommunikationssystemen ist von hohem wissenschaftlichem und wirtschaftlichem Interesse. Die stetige Fortentwicklung dieser Systeme, sowohl unter Aspekten der Hard- als auch der Software, hat ein neues Technologiezeitalter eingeläutet. Verschiedene Szenarien, auf optischen, drahtgebundenen und drahtlosen Technologien basierend, wurden für diese Anwendungen entwickelt. Im 60 GHz ISM-Band (57 GHz bis 65 GHz) ist wegen der hohen Absorptionsverluste bei dieser Frequenz eine Kurzstrecken-Kommunikation mit hoher Datenrate von besonders hohem Interesse. Die Realisierung solcher Systeme erfolgt aufgrund von Kosten- und Massenproduktionsaspekten auf Basis von SiGe-HBT und CMOS Technologien. Schlüsselparameter eines 60 GHz-Transceivers sind eine hohe Ausgangsleistung, niedrige Rauschzahl, geringer Stromverbrauch und niedrige Herstellungskosten. Um den gesamten Frequenzbereich des 60 GHz ISM-Bandes abdecken zu können, wurden zahlreiche Transceivertopologien weltweit diskutiert. Die verfügbare Technologie mit ihren Schlüsselparametern ft, fmax stellt hierbei eine wichtige Randbedingung dar. In dieser Arbeit werden Aspekte des 60 GHz-Transceiver-Designs unter Verwendung einer 0,25 μm SiGe-HBT- und einer 90 nm CMOS-Technologie untersucht. Zunächst wird die Modellierung von passiven und aktiven Komponenten diskutiert. Verschiedene Techniken zur Modellextraktion basierend auf Messungen und elektromagnetischen Simulationen werden gezeigt. Für die wichtigsten passiven Bauelemente werden skalierbare Modelle entwickelt, um das Entwurfsverfahren zu präzisieren. Im nächsten Schritt werden 60 GHz CMOS- und SiGe-HBT- Leistungsverstärker untersucht. Basierend auf diesen Studien wurden zwei HBT und zwei CMOS-Endstufen konzipiert, realisiert und gemessen. Infolge der Verfügbarkeit einer hochgenauen Bauelemente-Bibliothek, ausgereifter Entwurfstechniken und der Verifikation auf Basis von EM-Simulationen konnte an den gemessenen Leistungsverstärkern eine hohe Ausgangsleistung mit guter Effizienz nachgewiesen werden. Die Ergebnisse zeigen weiterhin eine gute Übereinstimmung von Simulationen mit Messungen. Weiterhin wurden auf Basis einer 90 nm CMOS Technologie ein Heterodyne und ein OOK Transceiver entwickelt. Der Heterodyne-Transceiver mit einer Zwischenfrequenz von 20 GHz genügt dabei dem IEEE 802.15.3c Standard und erreicht eine Performance auf Höhe des internationalen Standes von Wissenschaft und Technik. Für den OOK Sender wurde eine neue Topologie entwickelt. Bei diesem Konzept bilden Modulator und Leistungsverstärker eine Einheit, woraus Vorteile hinsichtlich Ausgangsleistung, Effizienz und Chipgröße resultieren. Mit dieser Schaltung wurde in einem Systemtest eine Übertragungsrate von 6 Gbps über eine Entfernung von 4 m erfolgreich nachgewiesen.The rise of high-data-rate hungry applications has brought a new dawn to telecommunication technologies in both hardware and software development aspects. Different scenarios, mainly based on optical, coaxial and wireless systems, have been developed for these multi-gigabit communication systems. In these scenarios, the wireless system is utilized for indoor and short-range communication, which can ease the requirements on RF power and noise figure of the transceivers. However, the demand for multi-gigabit communication imposes a broadband performance requirement upon these wireless transceivers. This broadband performance requirement can be within the range of 2 GHz to 10 GHz. In order to cover such a broad frequency range, different transceiver circuit topologies have been suggested by many circuit designers. Due to the high oxygen loss in the 60 GHz range this 57 GHz to 65 GHz ISM band has attracted attention for high speed short-range communication. Moreover, the newly emerged low cost technologies (like, CMOS and SiGe HBT) have further attracted the industry to explore this communication band. The main requirements for a 60 GHz transceiver are high output power, low noise figure, low power consumption and broadband performance. To cover the whole 57 GHz to 65 GHz frequency band, numerous transceiver topologies are under discussion. The key parameter ft, fmax of the available technology define the achievable system performance. In this thesis, multiple aspects of the 60 GHz transceiver design based on the 90 nm CMOS and 0.25 μm SiGe HBT designs have been investigated. First, the modeling of passive and active components is presented. These components include capacitors, inductors, transformers, transmission lines, transistors, matching networks and RF pads. Different techniques for model extraction based on measurements and electromagnetic simulations have been examined. For inductors, transformers and capacitors scalable models have been developed. Further, the design techniques of 60 GHz CMOS and SiGe HBT power amplifiers have been studied. Based on these studies, two HBT and two CMOS power amplifiers have been designed, realized and measured. Due to accurate modeling and design techniques, high performance and good agreement with simulation has been achieved. Finally, two different types of transmitters (Heterodyne and OOK) based on the CMOS technology have been developed. The heterodyne transceiver, with an IF frequency of around 20 GHz, has been designed based on the IEEE 802.15.3c standard. This transmitter has achieved state of the art results with respect to output power, conversion gain and efficiency with a small chip size and low power consumption. For the OOK transmitter, a novel topology has been developed. In this topology, the modulator and the power amplifier have been integrated into one circuit. Due to many advantages of this new topology, this transmitter achieves higher output power and efficiency compared with state-of-the-art results. Furthermore, the realized circuit has been utilized within a wireless system where more than 6 Gbps has been successfully transmitted over a 4 m distance

Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS

Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.Postprint (published version

Convergence of millimeter-wave and photonic interconnect systems for very-high-throughput digital communication applications

In the past, radio-frequency signals were commonly used for low-speed wireless electronic systems, and optical signals were used for multi-gigabit wired communication systems. However, as the emergence of new millimeter-wave technology introduces multi-gigabit transmission over a wireless radio-frequency channel, the borderline between radio-frequency and optical systems becomes blurred. As a result, there come ample opportunities to design and develop next-generation broadband systems to combine the advantages of these two technologies to overcome inherent limitations of various broadband end-to-end interconnect systems in signal generation, recovery, synchronization, and so on. For the transmission distances of a few centimeters to thousands of kilometers, the convergence of radio-frequency electronics and optics to build radio-over-fiber systems ushers in a new era of research for the upcoming very-high-throughput broadband services. Radio-over-fiber systems are believed to be the most promising solution to the backhaul transmission of the millimeter-wave wireless access networks, especially for the license-free, very-high-throughput 60-GHz band. Adopting radio-over-fiber systems in access or in-building networks can greatly extend the 60-GHz signal reach by using ultra-low loss optical fibers. However, such high frequency is difficult to generate in a straightforward way. In this dissertation, the novel techniques of homodyne and heterodyne optical-carrier suppressions for radio-over-fiber systems are investigated and various system architectures are designed to overcome these limitations of 60-GHz wireless access networks, bringing the popularization of multi-gigabit wireless networks to become closer to the reality. In addition to the advantages for the access networks, extremely high spectral efficiency, which is the most important parameter for long-haul networks, can be achieved by radio-over-fiber signal generation. As a result, the transmission performance of spectrally efficient radio-over-fiber signaling, including orthogonal frequency division multiplexing and orthogonal wavelength division multiplexing, is broadly and deeply investigated. On the other hand, radio-over-fiber is also used for the frequency synchronization that can resolve the performance limitation of wireless interconnect systems. A novel wireless interconnects assisted by radio-over-fiber subsystems is proposed in this dissertation. In conclusion, multiple advantageous facets of radio-over-fiber systems can be found in various levels of end-to-end interconnect systems. The rapid development of radio-over-fiber systems will quickly change the conventional appearance of modern communications.PhDCommittee Chair: Gee-Kung Chang; Committee Member: Bernard Kippelen; Committee Member: Shyh-Chiang Shen; Committee Member: Thomas K. Gaylord; Committee Member: Umakishore Ramachandra

Millimeter-scale RF Integrated Circuits and Antennas for Energy-efficient Wireless Sensor Nodes

Recently there has been increased demand for a millimeter-scale wireless sensor node for applications such as biomedical devices, defense, and surveillance. This form-factor is driven by a desire to be vanishingly small, injectable through a needle, or implantable through a minimally-invasive surgical procedure. Wireless communication is a necessity, but there are several challenges at the millimeter-scale wireless sensor node. One of the main challenges is external components like crystal reference and antenna become the bottleneck of realizing the mm-scale wireless sensor node device. A second challenge is power consumption of the electronics. At mm-scale, the micro-battery has limited capacity and small peak current. Moreover, the RF front-end circuits that operates at the highest frequency in the system will consume most of the power from the battery. Finally, as node volume reduces, there is a challenge of integrating the entire system together, in particular for the RF performance, because all components, including the battery and ICs, need to be placed in close proximity of the antenna. This research explores ways to implement low-power integrated circuits in an energy-constrained and volume constrained application. Three different prototypes are mainly conducted in the proposal. The first is a fully-encapsulated, autonomous, complete wireless sensor node with UWB transmitter in 10.6mm3 volume. It is the first time to demonstrate a full and stand-alone wireless sensing functionality with such a tiny integrated system. The second prototype is a low power GPS front-end receiver that supports burst-mode. A double super-heterodyne topology enables the reception of the three public GPS bands, L1, L2 and L5 simultaneously. The third prototype is an integrated rectangular slot loop antenna in a standard 0.13-μm BiCMOS technology. The antenna is efficiently designed to cover the bandwidth at 60 GHz band and easily satisfy the metal density rules and can be integrated with other circuitry in a standard process.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/143972/1/hskims_1.pd

Modulation, Coding, and Receiver Design for Gigabit mmWave Communication

While wireless communication has become an ubiquitous part of our daily life and the world around us, it has not been able yet to deliver the multi-gigabit throughput required for applications like high-definition video transmission or cellular backhaul communication. The throughput limitation of current wireless systems is mainly the result of a shortage of spectrum and the problem of congestion. Recent advancements in circuit design allow the realization of analog frontends for mmWave frequencies between 30GHz and 300GHz, making abundant unused spectrum accessible. However, the transition to mmWave carrier frequencies and GHz bandwidths comes with new challenges for wireless receiver design. Large variations of the channel conditions and high symbol rates require flexible but power-efficient receiver designs. This thesis investigates receiver algorithms and architectures that enable multi-gigabit mmWave communication. Using a system-level approach, the design options between low-power time-domain and power-hungry frequency-domain signal processing are explored. The system discussion is started with an analysis of the problem of parameter synchronization in mmWave systems and its impact on system design. The proposed synchronization architecture extends known synchronization techniques to provide greater flexibility regarding the operating environments and for system efficiency optimization. For frequency-selective environments, versatile single-carrier frequency domain equalization (SC-FDE) offers not only excellent channel equalization, but also the possibility to integrate additional baseband tasks without overhead. Hence, the high initial complexity of SC-FDE needs to be put in perspective to the complexity savings in the other parts of the baseband. Furthermore, an extension to the SC-FDE architecture is proposed that allows an adaptation of the equalization complexity by switching between a cyclic-prefix mode and a reduced block length overlap-save mode based on the delay spread. Approaching the problem of complexity adaptation from time-domain, a high-speed hardware architecture for the delayed decision feedback sequence estimation (DDFSE) algorithm is presented. DDFSE uses decision feedback to reduce the complexity of the sequence estimation and allows to set the system performance between the performance of full maximum-likelihood detection and pure decision feedback equalization. An implementation of the DDFSE architecture is demonstrated as part of an all-digital IEEE802.11ad baseband ASIC manufactured in 40nm CMOS. A flexible architecture for wideband mmWave receivers based on complex sub-sampling is presented. Complex sub-sampling combines the design advantages of sub-sampling receivers with the flexibility of direct-conversion receivers using a single passive component and a digital compensation scheme. Feasibility of the architecture is proven with a 16Gb/s hardware demonstrator. The demonstrator is used to explore the potential gain of non-equidistant constellations for high-throughput mmWave links. Specifically crafted amplitude phase-shift keying (APSK) modulation achieve 1dB average mutual information (AMI) advantage over quadrature amplitude modulation (QAM) in simulation and on the testbed hardware. The AMI advantage of APSK can be leveraged for a practical transmission using Polar codes which are trained specifically for the constellation