Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices

This thesis project involves the design and analysis of an 8-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC), designed for low- power applications such as bio-medical implants. The sampling rate for this ADC is 500 KS/s. The power consumption for the whole SAR ADC system was measured to be 2.1 uW. The novelty of this project is the proposal of an extremely energy efficient comparator architecture. The result is the design of a final ADC with reasonable sampling speed, accuracy and low power consumption. In this project, all the different subsystems have been designed at the transistor level with 45 nm CMOS technology. The logical circuit was designed using Verilog language. It was then synthesized and integrated in the overall system

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

A 12-bit, 40 msamples/s, low-power, low-area pipeline analog-to-digital converter in CMOS 0.18 mum technology.

With advancements in digital signal processing in recent years, the need for high-speed, high-resolution analog-to-digital converters (ADCs) which can be used in the analog front-end has been increasing. Some examples of these applications are image and video signal processing, wireless communications and asymmetrical digital subscriber line (ADSL). In CMOS integrated circuit design, it is desirable to integrate the digital circuit and the ADC in one microchip to reduce the cost of fabrication. Consequently the power dissipation and area of the ADCs are important design factors. The original contributions in this thesis are as follows. Since the performance of pipeline ADCs significantly depends on the op-amps and comparators circuits, the performance of various comparators is analyzed and the effect of op-amp topology on the performance of pipeline ADCs is investigated. This thesis also presents a novel architecture for design of low-power and low-area pipelined ADCs which will be more useful for very low voltage applications in the future. At the schematic level, a low-power CMOS implementation of the current-mode MDAC is presented and an improved voltage comparator is designed. With the proposed design and the optimization methodology it is possible to reduce power dissipation and area compared with conventional fully differential schemes.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .M64. Source: Masters Abstracts International, Volume: 43-01, page: 0281. Adviser: C. Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.Junta de Andalucía P09-TIC-5386Gobierno Español TEC2011-2830

Characterization of a 12-bit pipeline analog to digital converter

This thesis presents the characterization of the 12-bit pipeline analog-to-digital converter (ADC) designed by Mark Hale, Ph.D. graduate from the University of Tennessee. An overview of the pipeline ADC architecture is discussed first, and then the specifics of the testing procedure and results are detailed. The differential nonlinearity (DNL), integral nonlinearity (INL), DC offset error, and gain error for the pipeline ADC are the DC characteristics of interest. The DC characterization was performed in order to analyze the linearity of the ADC output over the analog input range. Additionally, the DNL and INL results were used to determine if the ADC exhibited undesirable effects, such as missed codes. The characterization was performed at room temperature using differential sinusoidal inputs. Labview was utilized to efficiently gather the digital output levels of the ADC, and Matlab was employed to compute the characteristics of the tested ADC. During the testing process several difficulties were encountered. Characterization results were negatively impacted by the presence of noise both at the output of the sample-and-hold and on the supply rails. Through iterative testing, the results improved. However, the effective number of bits for the tested ADC did not attain the desired 12-bits