47,638 research outputs found
Is a 4-bit synaptic weight resolution enough? - Constraints on enabling spike-timing dependent plasticity in neuromorphic hardware
Large-scale neuromorphic hardware systems typically bear the trade-off
between detail level and required chip resources. Especially when implementing
spike-timing-dependent plasticity, reduction in resources leads to limitations
as compared to floating point precision. By design, a natural modification that
saves resources would be reducing synaptic weight resolution. In this study, we
give an estimate for the impact of synaptic weight discretization on different
levels, ranging from random walks of individual weights to computer simulations
of spiking neural networks. The FACETS wafer-scale hardware system offers a
4-bit resolution of synaptic weights, which is shown to be sufficient within
the scope of our network benchmark. Our findings indicate that increasing the
resolution may not even be useful in light of further restrictions of
customized mixed-signal synapses. In addition, variations due to production
imperfections are investigated and shown to be uncritical in the context of the
presented study. Our results represent a general framework for setting up and
configuring hardware-constrained synapses. We suggest how weight discretization
could be considered for other backends dedicated to large-scale simulations.
Thus, our proposition of a good hardware verification practice may rise synergy
effects between hardware developers and neuroscientists
Shuttle passenger couch
Conceptual design and fabrication of a full scale shuttle passenger couch engineering model are reported. The model was utilized to verify anthropometric dimensions, reach dimensions, ingress/egress, couch operation, storage space, restraint locations, and crew acceptability. These data were then incorported in the design of the passenger couch verification model that underwent performance tests
Applying Formal Methods to Networking: Theory, Techniques and Applications
Despite its great importance, modern network infrastructure is remarkable for
the lack of rigor in its engineering. The Internet which began as a research
experiment was never designed to handle the users and applications it hosts
today. The lack of formalization of the Internet architecture meant limited
abstractions and modularity, especially for the control and management planes,
thus requiring for every new need a new protocol built from scratch. This led
to an unwieldy ossified Internet architecture resistant to any attempts at
formal verification, and an Internet culture where expediency and pragmatism
are favored over formal correctness. Fortunately, recent work in the space of
clean slate Internet design---especially, the software defined networking (SDN)
paradigm---offers the Internet community another chance to develop the right
kind of architecture and abstractions. This has also led to a great resurgence
in interest of applying formal methods to specification, verification, and
synthesis of networking protocols and applications. In this paper, we present a
self-contained tutorial of the formidable amount of work that has been done in
formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial
Smart technologies for effective reconfiguration: the FASTER approach
Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows
Framework for a space shuttle main engine health monitoring system
A framework developed for a health management system (HMS) which is directed at improving the safety of operation of the Space Shuttle Main Engine (SSME) is summarized. An emphasis was placed on near term technology through requirements to use existing SSME instrumentation and to demonstrate the HMS during SSME ground tests within five years. The HMS framework was developed through an analysis of SSME failure modes, fault detection algorithms, sensor technologies, and hardware architectures. A key feature of the HMS framework design is that a clear path from the ground test system to a flight HMS was maintained. Fault detection techniques based on time series, nonlinear regression, and clustering algorithms were developed and demonstrated on data from SSME ground test failures. The fault detection algorithms exhibited 100 percent detection of faults, had an extremely low false alarm rate, and were robust to sensor loss. These algorithms were incorporated into a hierarchical decision making strategy for overall assessment of SSME health. A preliminary design for a hardware architecture capable of supporting real time operation of the HMS functions was developed. Utilizing modular, commercial off-the-shelf components produced a reliable low cost design with the flexibility to incorporate advances in algorithm and sensor technology as they become available
JaxNet: Scalable Blockchain Network
Today's world is organized based on merit and value. A single global currency
that's decentralized is needed for a global economy. Bitcoin is a partial
solution to this need, however it suffers from scalability problems which
prevent it from being mass-adopted. Also, the deflationary nature of bitcoin
motivates people to hoard and speculate on them instead of using them for day
to day transactions. We propose a scalable, decentralized cryptocurrency that
is based on Proof of Work.The solution involves having parallel chains in a
closed network using a mechanism which rewards miners proportional to their
effort in maintaining the network.The proposed design introduces a novel
approach for solving scalability problem in blockchain network based on merged
mining.Comment: 55 pages. 10 figure
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