THOR:A Neuromorphic Processor with 7.29G TSOP2/mm2Js Energy-Throughput Efficiency

Neuromorphic computing using biologically inspired Spiking Neural Networks (SNNs) is a promising solution to meet Energy-Throughput (ET) efficiency needed for edge computing devices. Neuromorphic hardware architectures that emulate SNNs in analog/mixed-signal domains have been proposed to achieve order-of-magnitude higher energy efficiency than all-digital architectures, however at the expense of limited scalability, susceptibility to noise, complex verification, and poor flexibility. On the other hand, state-of-the-art digital neuromorphic architectures focus either on achieving high energy efficiency (Joules/synaptic operation (SOP)) or throughput efficiency (SOPs/second/area), resulting in poor ET efficiency. In this work, we present THOR, an all-digital neuromorphic processor with a novel memory hierarchy and neuron update architecture that addresses both energy consumption and throughput bottlenecks. We implemented THOR in 28nm FDSOI CMOS technology and our post-layout results demonstrate an ET efficiency of 7.29G TSOP2/mm2Js at 0.9V, 400 MHz, which represents a 3X improvement over state-of-the-art digital neuromorphic processors

Proceedings of the third International Workshop of the IFIP WG5.7

Contents of the papers presented at the international workshop deal with the wide variety of new and computer-based techniques for production planning and control that has become available to the scientific and industrial world in the past few years: formal modeling techniques, artificial neural networks, autonomous agent theory, genetic algorithms, chaos theory, fuzzy logic, simulated annealing, tabu search, simulation and so on. The approach, while being scientifically rigorous, is focused on the applicability to industrial environment

High level compilation for gate reconfigurable architectures

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 205-215).A continuing exponential increase in the number of programmable elements is turning management of gate-reconfigurable architectures as "glue logic" into an intractable problem; it is past time to raise this abstraction level. The physical hardware in gate-reconfigurable architectures is all low level - individual wires, bit-level functions, and single bit registers - hence one should look to the fetch-decode-execute machinery of traditional computers for higher level abstractions. Ordinary computers have machine-level architectural mechanisms that interpret instructions - instructions that are generated by a high-level compiler. Efficiently moving up to the next abstraction level requires leveraging these mechanisms without introducing the overhead of machine-level interpretation. In this dissertation, I solve this fundamental problem by specializing architectural mechanisms with respect to input programs. This solution is the key to efficient compilation of high-level programs to gate reconfigurable architectures. My approach to specialization includes several novel techniques. I develop, with others, extensive bitwidth analyses that apply to registers, pointers, and arrays. I use pointer analysis and memory disambiguation to target devices with blocks of embedded memory. My approach to memory parallelization generates a spatial hierarchy that enables easier-to-synthesize logic state machines with smaller circuits and no long wires.(cont.) My space-time scheduling approach integrates the techniques of high-level synthesis with the static routing concepts developed for single-chip multiprocessors. Using DeepC, a prototype compiler demonstrating my thesis, I compile a new benchmark suite to Xilinx Virtex FPGAs. Resulting performance is comparable to a custom MIPS processor, with smaller area (40 percent on average), higher evaluation speeds (2.4x), and lower energy (18x) and energy-delay (45x). Specialization of advanced mechanisms results in additional speedup, scaling with hardware area, at the expense of power. For comparison, I also target IBM's standard cell SA-27E process and the RAW microprocessor. Results include sensitivity analysis to the different mechanisms specialized and a grand comparison between alternate targets.by Jonathan William Babb.Ph.D

Embedded System Design

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues

On a Joint Physical Layer and Medium Access Control Sublayer Design for Efficient Wireless Sensor Networks and Applications

Wireless sensor networks (WSNs) are distributed networks comprising small sensing devices equipped with a processor, memory, power source, and often with the capability for short range wireless communication. These networks are used in various applications, and have created interest in WSN research and commercial uses, including industrial, scientific, household, military, medical and environmental domains. These initiatives have also been stimulated by the finalisation of the IEEE 802.15.4 standard, which defines the medium access control (MAC) and physical layer (PHY) for low-rate wireless personal area networks (LR-WPAN). Future applications may require large WSNs consisting of huge numbers of inexpensive wireless sensor nodes with limited resources (energy, bandwidth), operating in harsh environmental conditions. WSNs must perform reliably despite novel resource constraints including limited bandwidth, channel errors, and nodes that have limited operating energy. Improving resource utilisation and quality-of-service (QoS), in terms of reliable connectivity and energy efficiency, are major challenges in WSNs. Hence, the development of new WSN applications with severe resource constraints will require innovative solutions to overcome the above issues as well as improving the robustness of network components, and developing sustainable and cost effective implementation models. The main purpose of this research is to investigate methods for improving the performance of WSNs to maintain reliable network connectivity, scalability and energy efficiency. The study focuses on the IEEE 802.15.4 MAC/PHY layers and the carrier sense multiple access with collision avoidance (CSMA/CA) based networks. First, transmission power control (TPC) is investigated in multi and single-hop WSNs using typical hardware platform parameters via simulation and numerical analysis. A novel approach to testing TPC at the physical layer is developed, and results show that contrary to what has been reported from previous studies, in multi-hop networks TPC does not save energy. Next, the network initialization/self-configuration phase is addressed through investigation of the 802.15.4 MAC beacon interval setting and the number of associating nodes, in terms of association delay with the coordinator. The results raise doubt whether that the association energy consumption will outweigh the benefit of duty cycle power management for larger beacon intervals as the number of associating nodes increases. The third main contribution of this thesis is a new cross layer (PHY-MAC) design to improve network energy efficiency, reliability and scalability by minimising packet collisions due to hidden nodes. This is undertaken in response to findings in this thesis on the IEEE 802.15.4 MAC performance in the presence of hidden nodes. Specifically, simulation results show that it is the random backoff exponent that is of paramount importance for resolving collisions and not the number of times the channel is sensed before transmitting. However, the random backoff is ineffective in the presence of hidden nodes. The proposed design uses a new algorithm to increase the sensing coverage area, and therefore greatly reduces the chance of packet collisions due to hidden nodes. Moreover, the design uses a new dynamic transmission power control (TPC) to further reduce energy consumption and interference. The above proposed changes can smoothly coexist with the legacy 802.15.4 CSMA/CA. Finally, an improved two dimensional discrete time Markov chain model is proposed to capture the performance of the slotted 802.15.4 CSMA/CA. This model rectifies minor issues apparent in previous studies. The relationship derived for the successful transmission probability, throughput and average energy consumption, will provide better performance predictions. It will also offer greater insight into the strengths and weaknesses of the MAC operation, and possible enhancement opportunities. Overall, the work presented in this thesis provides several significant insights into WSN performance improvements with both existing protocols and newly designed protocols. Finally, some of the numerous challenges for future research are described

Foundations of Software Science and Computation Structures

This open access book constitutes the proceedings of the 22nd International Conference on Foundations of Software Science and Computational Structures, FOSSACS 2019, which took place in Prague, Czech Republic, in April 2019, held as part of the European Joint Conference on Theory and Practice of Software, ETAPS 2019. The 29 papers presented in this volume were carefully reviewed and selected from 85 submissions. They deal with foundational research with a clear significance for software science