35 research outputs found
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The distributed computer system
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University
Hierarchical architecture design and simulation environment
The Hierarchical Architectural design and Simulation Environment (HASE)is
intended as a flexible tool for computer architects who wish to experiment with
alternative architectural configurations and design parameters. HASE is both
a design environment and a simulator. Architecture components are described
by a hierarchical library of objects defined in terms of an object oriented simulation language. HASE instantiates these objects to simulate and animate the
execution of a computer architecture. An event trace generated by the simulator
therefore describes the interaction between architecture components, for example,
fetch stages, address and data buses, sequencers, instruction buffers and register
files. The objects can model physical components at different abstraction levels,
eg. PMS (processor memory switch), ISP (instruction set processor) and RTL
(register transfer level). HASE applies the concepts of inheritance, encapsulation
and polymorphism associated with object orientation, to simplify the design and
implementation of an architecture simulation that models component operations
at different abstraction levels. For example, HASE can probe the performance
of a processor's floating point unit, executing a multiplication operation, at a
lower level of abstraction, i.e. the RTL, whilst simulating remaining architecture
components at a PMS level of abstraction. By adopting this approach, HASE
returns a more meaningful and relevant event trace from an architecture simulation. Furthermore, an animator visualises the simulation's event trace to clarify
the collaborations and interactions between architecture components. The prototype version of HASE is based on GSS (Graphical Support System), and DEMOS
(Discrete Event Modelling On Simula)
The formal verification of generic interpreters
The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does
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NBS monograph
From Introduction: "This is the third in a planned series of reports involving selective literature reviews of research and development requirements and areas of continuing R & D concern in the computer and information sciences and technologies.
Towards the formal specification of the requirements and design of a processor interface unit
Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.
Research-study of a self-organizing computer
It is shown that a self organizing system has two main components: an organizable physical part, and a programing part. This report presents the organizable part in the form of a programable hardware and its programing language
Data systems elements technology assessment and system specifications, issue no. 2
The ability to satisfy the objectives of future NASA Office of Applications programs is dependent on technology advances in a number of areas of data systems. The hardware and software technology of end-to-end systems (data processing elements through ground processing, dissemination, and presentation) are examined in terms of state of the art, trends, and projected developments in the 1980 to 1985 timeframe. Capability is considered in terms of elements that are either commercially available or that can be implemented from commercially available components with minimal development
Increasing the Performance and Predictability of the Code Execution on an Embedded Java Platform
This thesis explores the execution of object-oriented code on an embedded Java platform. It presents established and derives new approaches for the implementation of high-level object-oriented functionality and commonly expected system services. The goal of the developed techniques is the provision of the architectural base for an efficient and predictable code execution.
The research vehicle of this thesis is the Java-programmed SHAP platform. It consists of its platform tool chain and the highly-customizable SHAP bytecode processor. SHAP offers a fully operational embedded CLDC environment, in which the proposed techniques have been implemented, verified, and evaluated.
Two strands are followed to achieve the goal of this thesis. First of all, the sequential execution of bytecode is optimized through a joint effort of an optimizing offline linker and an on-chip application loader. Additionally, SHAP pioneers a reference coloring mechanism, which enables a constant-time interface method dispatch that need not be backed a large sparse dispatch table.
Secondly, this thesis explores the implementation of essential system services within designated concurrent hardware modules. This effort is necessary to decouple the computational progress of the user application from the interference induced by time-sharing software implementations of these services. The concrete contributions comprise
a spill-free, on-chip stack; a predictable method cache; and a concurrent garbage collection.
Each approached means is described and evaluated after the relevant state of the art has been reviewed. This review is not limited to preceding small embedded approaches but also includes techniques that have proven successful on larger-scale platforms. The other way around, the chances that these platforms may benefit from the techniques developed for SHAP are discussed