Compact low-power calibration mini-DACs for neural arrays with programmable weights

This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8% or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons.Gobierno de España TIC1999-0446-C02-02, TIC2000-0406-P4-05, FIT-07000/2002/921, TIC2002-10878-EEuropean Union IST- 2001-3412

Dataset for neutron and gamma-ray pulse shape discrimination

The publicly accessible dataset includes neutron and gamma-ray pulse signals for conducting pulse shape discrimination experiments. Several traditional and recently proposed pulse shape discrimination algorithms are utilized to evaluate the performance of pulse shape discrimination under raw pulse signals and noise-enhanced datasets. These algorithms comprise zero-crossing (ZC), charge comparison (CC), falling edge percentage slope (FEPS), frequency gradient analysis (FGA), pulse-coupled neural network (PCNN), ladder gradient (LG), and het-erogeneous quasi-continuous spiking cortical model (HQC-SCM). In addition to the pulse signals, this dataset includes the source code for all the aforementioned pulse shape discrimination methods. Moreover, the dataset provides the source code for schematic pulse shape discrimination performance evaluation and anti-noise performance evaluation. This feature enables researchers to evaluate the performance of these methods using standard procedures and assess their anti-noise ability under various noise conditions. In conclusion, this dataset offers a comprehensive set of resources for conducting pulse shape discrimination experiments and evaluating the performance of various pulse shape discrimination methods under different noise scenarios.Comment: 11 pages,10 figure

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16x16 has been implemented with programmable kernel size of up to 16x16. The chip has been fabricated in a standard 0.35- m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.Commission of the European Communities IST-2001-34124 (CAVIAR)Commission of the European Communities 216777 (NABAB)Ministerio de Educación y Ciencia TIC-2000-0406-P4Ministerio de Educación y Ciencia TIC-2003-08164-C03-01Ministerio de Educación y Ciencia TEC2006-11730-C03-01Junta de Andalucía TIC-141

Neuromorphic silicon neuron circuits

23 páginas, 21 figuras, 2 tablas.-- et al.Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.This work was supported by the EU ERC grant 257219 (neuroP), the EU ICT FP7 grants 231467 (eMorph), 216777 (NABAB), 231168 (SCANDLE), 15879 (FACETS), by the Swiss National Science Foundation grant 119973 (SoundRec), by the UK EPSRC grant no. EP/C010841/1, by the Spanish grants (with support from the European Regional Development Fund) TEC2006-11730-C03-01 (SAMANTA2), TEC2009-10639-C04-01 (VULCANO) Andalusian grant num. P06TIC01417 (Brain System), and by the Australian Research Council grants num. DP0343654 and num. DP0881219.Peer Reviewe

TGFβ signaling is associated with changes in inflammatory gene expression and perineuronal net degradation around inhibitory neurons following various neurological insults.

Brain damage due to stroke or traumatic brain injury (TBI), both leading causes of serious long-term disability, often leads to the development of epilepsy. Patients who develop post-injury epilepsy tend to have poor functional outcomes. Emerging evidence highlights a potential role for blood-brain barrier (BBB) dysfunction in the development of post-injury epilepsy. However, common mechanisms underlying the pathological hyperexcitability are largely unknown. Here, we show that comparative transcriptome analyses predict remodeling of extracellular matrix (ECM) as a common response to different types of injuries. ECM-related transcriptional changes were induced by the serum protein albumin via TGFβ signaling in primary astrocytes. In accordance with transcriptional responses, we found persistent degradation of protective ECM structures called perineuronal nets (PNNs) around fast-spiking inhibitory interneurons, in a rat model of TBI as well as in brains of human epileptic patients. Exposure of a naïve brain to albumin was sufficient to induce the transcriptional and translational upregulation of molecules related to ECM remodeling and the persistent breakdown of PNNs around fast-spiking inhibitory interneurons, which was contingent on TGFβ signaling activation. Our findings provide insights on how albumin extravasation that occurs upon BBB dysfunction in various brain injuries can predispose neural circuitry to the development of chronic inhibition deficits

Pulse shape discrimination based on the Tempotron: a powerful classifier on GPU

This study introduces the Tempotron, a powerful classifier based on a third-generation neural network model, for pulse shape discrimination. By eliminating the need for manual feature extraction, the Tempotron model can process pulse signals directly, generating discrimination results based on learned prior knowledge. The study performed experiments using GPU acceleration, resulting in over a 500 times speedup compared to the CPU-based model, and investigated the impact of noise augmentation on the Tempotron's performance. Experimental results showed that the Tempotron is a potent classifier capable of achieving high discrimination accuracy. Furthermore, analyzing the neural activity of Tempotron during training shed light on its learning characteristics and aided in selecting the Tempotron's hyperparameters. The dataset used in this study and the source code of the GPU-based Tempotron are publicly available on GitHub at https://github.com/HaoranLiu507/TempotronGPU.Comment: 14 pages,7 figure