Next generation earth‑to‑space telecommand coding and synchronization: ground system design, optimization and software implementation

The Consultative Committee for Space Data Systems, followed by all national and international space agencies, has updated the Telecommand Coding and Synchronization sublayer to introduce new powerful low-density parity-check (LDPC) codes. Their large coding gains significantly improve the system performance and allow new Telecommand services and profiles with higher bit rates and volumes. In this paper, we focus on the Telecommand transmitter implementation in the Ground Station baseband segment. First, we discuss the most important blocks and we focus on the most critical one, i.e., the LDPC encoder. We present and analyze two techniques, one based on a Shift Register Adder Accumulator and the other on Winograd convolution both exploiting the block circulant nature of the LDPC matrix. We show that these techniques provide a significant complexity reduction with respect to the usual encoder mapping, thus allowing to obtain high uplink bit rates. We then discuss the choice of a proper hardware or software platform, and we show that a Central Processing Unit-based software solution is able to achieve the high bit rates requested by the new Telecommand applications. Finally, we present the results of a set of tests on the real-time software implementation of the new system, comparing the performance achievable with the different encoding options

FPGA Implementation of encoders for CCSDS Low-Density Parity-Check (LDPC) codes.

Η παρούσα διπλωματική εργασία παρουσιάζει την υλοποίηση με τεχνολογία FPGA αλγορίθμων κωδικοποίησης καναλιού που έχουν προτυποποιηθεί από τον οργανισμό CCSDS για χρήση σε διαστημικές επικοινωνίες. Ο CCSDS προτείνει δύο κατηγορίες κωδίκων για εφαρμογές τηλεμετρίας: μία για επικοινωνίες στο εγγύς (near-earth) διάστημα (π.χ. δορυφορικές επικοινωνίες) και άλλη μια για επικοινωνίες βαθέος διαστήματος (deep-space), με χαρακτηριστικά η κάθε μία βελτιστοποιημένα ως προς το πεδίο εφαρμογής τους. Και στις δύο περιπτώσεις, οι κώδικες είναι γραμμικοί μπλοκ κώδικες με μεγάλο μέγεθος μπλοκ και πίνακα ισοτιμίας με χαμηλή πυκνότητα (LDPC). Στην παρούσα εργασία, γίνεται εκμετάλλευση της δομής των πινάκων-γεννητόρων των κωδίκων deep-space προκειμένου να μεγιστοποιηθεί η απόδοση. Προκύπτουν δύο ειδών παραλληλίες στη δομή των εν λόγω πινάκων, η ταυτόχρονη αξιοποίηση των οποίων οδηγεί σε βελτίωση των επιδόσεων με ελαχιστοποίηση των καταναλισκόμενων πόρων. Αντίστοιχα στην περίπτωση του κώδικα near-earth, περιγράφεται μια αποδοτική μέθοδος στη σχεδίαση των επί μέρους οντοτήτων του κυκλώματος που βελτιστοποιεί την αξιοποίηση των πόρων, σε σχέση με γνωστές λύσεις. Η περιγραφή των κωδικοποιητών σε VHDL επαληθεύεται ως προς την ορθή της σχεδίαση με προσομοιώσεις για όλες τις υποστηριζόμενες περιπτώσεις, όπου απαιτείται η μέγιστη κάλυψη κώδικα (code coverage). Τέλος, το σχέδιο επαλήθευσης περιλαμβάνει την επίδειξη λειτουργίας σε ένα ενσωματωμένο σύστημα υλοποιημένο στην κάρτα XUPV505-LX110T, όπου καταγράφονται και οι πραγματικές επιδόσεις του συστήματος, όπου βρίσκονται στην περιοχή των μερικών Gbps. Η παρούσα υλοποίηση προκύπτει ότι είναι η ταχύτερη για την συγκεκριμένη οικογένεια LDPC κωδικών, που έχει επιτευχθεί μέχρι σήμερα.The FPGA implementation of LDPC encoders for channel codes standardized by CCSDS for space communication applications is described in this work. CCSDS suggests two classes of channel codes for telemetry applications: one for near-earth and another for deep-space communications, each one optimized for the demands of the specific field. In both cases, the specification concerns linear block codes with large block size and sparse generator matrices. Regarding near-earth codes, the specification describes a Euclidean geometry based (8160,7136) LDPC code at rate 7/8, while in the deep-space case, 9 codes are defined which are the combination of thee block lengths (1024,4096,16384 bits) with three rates (½, 2/3, 4/5), sharing a common mathematical description. This fact enables the VHDL description of a common encoder for all of them. The generator matrices of these codes possess considerable structure which facilitates implementation. Concerning deep-space codes generator matrices, parallelism extends over two dimensions, which can be exploited concurrently to optimize timing performance and at the same time minimize resource utilization. The price to be paid however is increased latency, which can be mitigated by the pipelined operation of the output interface. VHDL description of the encoder is generic, allowing the easy modification of the code parameters (block size, rate), the amount of parallelism in each dimension and the input-output bus width, leading to different performance-latency balances. Also in the case of the near-earth code, an efficient design of the encoder's sub-entities is described, leading to resources utilization optimizations, compared to existing implementations. The encoder in this case is designed for 16-bit input-output bus. All described encoders input-output is performed on AMBA AXI-4 Stream compliant interfaces, facilitating their integration in an embedded system's design and communication with standard FIFO interfaces. The encoders' operation is optimal in that an uninterrupted flow of data is provided on the output interface, without idle cycles. The only exception is the near-earth encoder for which just one idle cycle every 513 is inserted. The correctness of the VHDL description's is validated by functional simulation for all supported cases, where 100% code coverage is demanded. The verification plan includes also the demonstration of real-time operation of the encoders in an integrated system implemented on a XUPV505-LX110T development board, where the actual performance of the encoders is recorded and lies in the multi-Gbps range. Finally, the proposed encoders are shown to be the fastest stream-oriented implementations for the specified family of LDPC codes, with minimal resource utilization

Optimization of a Coded-Modulation System with Shaped Constellation

Conventional communication systems transmit signals that are selected from a signal constellation with uniform probability. However, information-theoretic results suggest that performance may be improved by shaping the constellation such that lower-energy signals are selected more frequently than higher-energy signals. This dissertation presents an energy efficient approach for shaping the constellations used by coded-modulation systems. The focus is on designing shaping techniques for systems that use a combination of amplitude phase shift keying (APSK) and low-density parity check (LDPC) coding. Such a combination is typical of modern satellite communications, such as the system used by the DVB-S2 standard.;The system implementation requires that a subset of the bits at the output of the LDPC encoder are passed through a nonlinear shaping encoder whose output bits are more likely to be a zero than a one. The constellation is partitioned into a plurality of sub-constellations, each with a different average signal energy, and the shaping bits are used to select the sub-constellation. An iterative receiver exchanges soft information among the demodulator, LDPC decoder, and shaping decoder. Parameters associated with the modulation and shaping code are optimized with respect to information rate, while the design of the LDPC code is optimized for the shaped modulation with the assistance of extrinsic-information transfer (EXIT) charts. The rule for labeling the constellation with bits is optimized using a novel hybrid cost function and a binary switching algorithm.;Simulation results show that the combination of constellation shaping, LDPC code optimization, and optimized bit labeling can achieve a gain in excess of 1 dB in an additive white Gaussian noise (AWGN) channel at a rate of 3 bits/symbol compared with a system that adheres directly to the DVB-S2 standard

Compute-and-Forward Relay Networks with Asynchronous, Mobile, and Delay-Sensitive Users

We consider a wireless network consisting of multiple source nodes, a set of relays and a destination node. Suppose the sources transmit their messages simultaneously to the relays and the destination aims to decode all the messages. At the physical layer, a conventional approach would be for the relay to decode the individual message one at a time while treating rest of the messages as interference. Compute-and-forward is a novel strategy which attempts to turn the situation around by treating the interference as a constructive phenomenon. In compute-and-forward, each relay attempts to directly compute a combination of the transmitted messages and then forwards it to the destination. Upon receiving the combinations of messages from the relays, the destination can recover all the messages by solving the received equations. When identical lattice codes are employed at the sources, error correction to integer combination of messages is a viable option by exploiting the algebraic structure of lattice codes. Therefore, compute-and-forward with lattice codes enables the relay to manage interference and perform error correction concurrently. It is shown that compute-and-forward exhibits substantial improvement in the achievable rate compared with other state-of-the-art schemes for medium to high signal-to-noise ratio regime. Despite several results that show the excellent performance of compute-and-forward, there are still important challenges to overcome before we can utilize compute-and- forward in practice. Some important challenges include the assumptions of \perfect timing synchronization "and \quasi-static fading", since these assumptions rarely hold in realistic wireless channels. So far, there are no conclusive answers to whether compute-and-forward can still provide substantial gains even when these assumptions are removed. When lattice codewords are misaligned and mixed up, decoding integer combination of messages is not straightforward since the linearity of lattice codes is generally not invariant to time shift. When channel exhibits time selectivity, it brings challenges to compute-and-forward since the linearity of lattice codes does not suit the time varying nature of the channel. Another challenge comes from the emerging technologies for future 5G communication, e.g., autonomous driving and virtual reality, where low-latency communication with high reliability is necessary. In this regard, powerful short channel codes with reasonable encoding/decoding complexity are indispensable. Although there are fruitful results on designing short channel codes for point-to-point communication, studies on short code design specifically for compute-and-forward are rarely found. The objective of this dissertation is threefold. First, we study compute-and-forward with timing-asynchronous users. Second, we consider the problem of compute-and- forward over block-fading channels. Finally, the problem of compute-and-forward for low-latency communication is studied. Throughout the dissertation, the research methods and proposed remedies will center around the design of lattice codes in order to facilitate the use of compute-and-forward in the presence of these challenges